Discrete 3D Memory Architecture with Segmented BEOL Structures
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Solution Overview
Problem
Integrated three-dimensional memory (3D-M) devices have high costs and reduced array efficiency due to the integration of peripheral-circuit components with 3D-M arrays, which increases manufacturing complexity and degrades performance.
Innovation Solution
A discrete 3D-M architecture is proposed, where the 3D-array die and peripheral-circuit die are separate, with peripheral-circuit components such as read/write-voltage generators and address/data translators located on a 2D peripheral-circuit die, allowing for different BEOL structures and interconnect materials that improve efficiency and reduce costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If peripheral-circuit components are integrated with 3D-M arrays on the same die, then device functionality is achieved, but array efficiency decreases and production costs increase
Solution Approach 1:
The patent divides the memory system into separate components: 3D-M array dice and peripheral-circuit dice. This segmentation allows the memory array to be optimized for high-density storage while peripheral circuits are optimized for their specific functions, thereby improving array efficiency to over 40% while maintaining full device functionality through inter-die connections.
Solution Approach 2:
The patent extracts peripheral-circuit components from the 3D-M array die and places them on separate peripheral-circuit dice. This extraction eliminates the space overhead and performance degradation caused by integrating peripheral circuits with the memory array, allowing the array to achieve higher efficiency while peripheral circuits use optimized BEOL structures.
2Reliability
If peripheral-circuit components are integrated with 3D-M arrays, then device functionality is achieved, but production costs increase
Solution Approach 1:
By segmenting the memory system into separate 3D-M array dice and peripheral-circuit dice, the patent enables independent manufacturing optimization. The 3D-M arrays can be produced using high-density 3D stacking techniques while peripheral circuits use conventional 2-D planar processes, reducing overall production costs while maintaining device functionality through standard inter-die packaging.
3Productivity
If different BEOL structures are used for 3D-M arrays and peripheral circuits, then manufacturing efficiency improves, but interconnect compatibility becomes challenging
Solution Approach 1:
The patent uses the package substrate as an intermediary that provides standardized interconnect interfaces between 3D-M array dice and peripheral-circuit dice. This intermediary layer with its controlled impedance traces and bonding pads enables compatibility between different BEOL structures, allowing manufacturing efficiency to improve while interconnect complexity is managed through standardized packaging techniques.
Data Source
AI summary
The present invention discloses a discrete three-dimensional memory (3D-M). It comprises at least a 3D-array die and at least a peripheral-circuit die. At least a peripheral-circuit component of the 3D-M is located on the peripheral-circuit die instead of the 3D-array die. The 3D-array die and the peripheral-circuit die have substantially different back-end-of-line (BEOL) structures, e.g. different number of BEOL layers, different number of interconnect layers, and/or different interconnect materials.