Discrete 3D Processor With Split Memory-Logic Die Architecture
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Solution Overview
Problem
Conventional processors face inefficiencies due to limited computational density and complexity, inability to perform non-arithmetic functions, and high costs associated with integrating two-dimensional and three-dimensional circuits, leading to slow performance in mathematical computing, computer simulation, pattern processing, and neural networks.
Innovation Solution
A discrete 3-D processor design that separates two-dimensional and three-dimensional circuits into different dice, allowing for optimized manufacturing and functionality, with a memory die and logic die connected by inter-die connections, enabling efficient computation and re-configurable capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If two-dimensional and three-dimensional circuits are integrated into a single processor die, then computational density and processing power are improved, but manufacturing complexity and cost increase significantly
Solution Approach 1:
The processor is divided into separate two-dimensional logic circuit die and three-dimensional memory circuit die, allowing each to be manufactured independently using optimized processes, then combined through inter-die connections to achieve high computational density without integrated manufacturing complexity
Solution Approach 2:
Inter-die connection structures serve as intermediaries between the 2-D logic die and 3-D memory die, enabling communication and data transfer while allowing each die to be manufactured separately with different process optimizations
2Ease of manufacture
If conventional two-dimensional integration is used, then manufacturing is simpler and less costly, but computational density and processing speed are limited
Solution Approach 1:
The memory circuit transitions from two-dimensional planar integration to three-dimensional stacked architecture, increasing storage capacity and computational density vertically above the logic circuit die without increasing the footprint area
3Ease of manufacture
If processor and external memory are separated as in von Neumann architecture, then manufacturing is easier, but data transfer bandwidth and efficiency are limited
Solution Approach 1:
The processor logic circuits and memory circuits are merged into a single integrated processor die through inter-die connections, creating a unified processing-memory system that eliminates external memory bottlenecks while maintaining separate manufacturing advantages
Data Source
AI summary
A discrete three-dimensional (3-D) processor comprises communicatively coupled first and second dice. The first die comprises memory arrays, whereas the second die comprises at least a non-memory circuit and at least an off-die peripheral-circuit component of the memory arrays. The first and second dice have substantially different structures, more particularly back-end-of-line (BEOL) structures.