Discrete Active Area Patterning With Multi-Layer Mask Etching

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Solution Overview

Problem

The challenge in semiconductor manufacturing is forming small-sized discrete active areas in dynamic random-access memories, as the feature size approaches the physical limit of optical photolithography, making it difficult to increase storage density and yield due to limitations in photolithography and etching technologies.

Innovation Solution

A semiconductor structure manufacturing method involving multiple mask layers with strategically designed strip-shaped patterns, where layer-by-layer etching using these masks forms discrete active areas, reducing manufacturing difficulty and improving production capacity and yield.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If photolithography and etching technologies are used to form small-sized discrete active areas, then storage density can be increased, but manufacturing difficulty increases and yield decreases due to approaching physical limits

Engineering Contradiction:
Improvestorage densityVSAvoidfeature size precision
Core Design Contradiction:
Quantity of substanceVSManufacturing precision

Solution Approach 1:

The patent divides the formation of discrete active areas into multiple patterning steps using sequential mask layers. Instead of attempting to directly pattern small-sized discrete active areas in a single photolithography step, the method segments the process into forming continuous active areas first, then using multiple mask layers (second and third mask layers) to progressively divide and separate them into discrete regions. This segmentation approach allows each step to operate at larger, more controllable dimensions while achieving the final small feature sizes, thereby resolving the contradiction between increasing storage density and maintaining manufacturing precision.

Inventive Principle:
Principle #1Segmentation

2Quantity of substance

If photolithography and etching technologies are used to form small-sized discrete active areas, then storage density can be increased, but manufacturing complexity increases

Engineering Contradiction:
Improvestorage densityVSAvoidmanufacturing process complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by first forming continuous active areas using a first mask layer before introducing subsequent mask layers to create discrete regions. The second and third mask layers are designed with patterns that overlap and work together to define the final discrete active area locations. This preliminary formation of continuous structures simplifies the overall process by establishing a base pattern that guides subsequent patterning steps, reducing manufacturing complexity while achieving high storage density.

Inventive Principle:
Principle #10Preliminary action

3Ease of manufacture

If conventional photolithography is used, then manufacturing process is simple, but productivity decreases due to inability to form small feature sizes efficiently

Engineering Contradiction:
Improveprocess simplicityVSAvoidproduction capacity
Core Design Contradiction:
Ease of manufactureVSProductivity

Solution Approach 1:

The patent transitions from two-dimensional planar patterning to three-dimensional multi-layer mask structuring. By introducing vertical stacking of multiple mask layers (first, second, and third mask layers) with overlapping patterns, the method achieves small feature size discrete active areas that cannot be obtained through conventional single-layer photolithography. This dimensional transition enables higher production capacity and storage density while maintaining process simplicity through systematic layer-by-layer fabrication.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS11972953B2Semiconductor structure and manufacturing method thereof
Publication Date: 2024.04.30 CHANGXIN MEMORY TECH INC
  • US11972953B2 patent drawing
  • US11972953B2 patent drawing
  • US11972953B2 patent drawing

AI summary

A semiconductor structure and a manufacturing method thereof are provided. The method includes: providing a substrate; forming, on the substrate, a first mask layer having a plurality of strip-shaped first patterns arranged in parallel; forming, on the first mask layer, a second mask layer having a plurality of strip-shaped second patterns arranged in parallel; forming, on the second mask layer, a third mask layer having a plurality of strip-shaped third patterns arranged in parallel, the second patterns overlap with the third patterns, and the second patterns and the third patterns are configured to sever the first patterns at predetermined positions; and performing layer-by-layer etching, using the first mask layer, the second mask layer, and the third mask layer as masks to transfer the first patterns, the second patterns, and the third patterns to the substrate to form an array of discrete active areas.