Discrete AuSn Bonding Elements for LED Submounts
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Solution Overview
Problem
The existing semiconductor light emitting apparatus experiences bonding defects due to burrs and uneven AuSn eutectic bonding layers, leading to fluctuations in heat resistance and forward voltage, and potentially resulting in short-circuiting and defective light emitting characteristics.
Innovation Solution
The use of discrete, one-dimensionally arranged AuSn layer elements with minimal spacing, and the application of AuSn-phobic Cr layers to prevent protrusion, ensures a stable and uniform bonding area between the semiconductor light emitting element and the substrate, reducing bonding defects and improving thermal integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If continuous AuSn layers are formed by lift-off process, then the bonding process can be completed, but burrs are created on the edges leading to uneven bonding layers and bonding defects
Solution Approach 1:
The patent divides the continuous AuSn bonding layer into discrete AuSn layer elements arranged in a one-dimensional pattern. This segmentation prevents the formation of burrs along the entire edge, limiting burr creation to only the ends of the discrete elements, thereby significantly reducing unevenness and bonding defects while maintaining manufacturability through standard lift-off processes.
2Manufacturing precision
If discrete AuSn layer elements are used, then bonding defects are reduced, but the bonding area may be decreased
Solution Approach 1:
The patent combines multiple discrete AuSn layer elements into a unified one-dimensionally arranged pattern that collectively provides sufficient bonding area. The elements are positioned and sized such that their combined area meets the bonding requirements while their discrete nature prevents burr formation along edges, achieving both reduced bonding defects and adequate bonding area.
3Reliability
If AuSn layers are made slender to match electrode dimensions, then heat resistance decreases and forward voltage fluctuation is suppressed, but the bonding area is reduced leading to defective bonding
Solution Approach 1:
The patent transitions from considering bonding layer dimensions in two dimensions (width and length) to utilizing a one-dimensional arrangement of discrete elements. This dimensional approach allows the bonding layers to be slender (reducing heat resistance and forward voltage fluctuation) while the collective arrangement of multiple elements provides sufficient total bonding area to prevent defective bonding.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces bonding defects, stabilizes heat resistance and forward voltage, and enhances light emitting characteristics by increasing the bonding area and preventing short-circuiting.
Implementation Method 1
the uppermost Au layers of the AuSn layer 31-1, 31-2, ···, 31-6 and 32 of the submount substrate 2 are eutectic with the uppermost Au layers of the p-side electrodes 11-1, 11-2, ···, 11-6 and the n-side electrode 12 of the LED element 1 to form AuSn eutectic bonding layer 31' -1, 31' -2, ···, 31' -6 and 32'
Implementation Method 2
the LED element 1 of Figs. 1A and 1B is faced down in a thermal-pressuring process on the submount substrate 2 of Figs. 2A and 2B
Data Source
Figure 1A~3B
Figure 4A~4D
Figure 5A~5C
AI summary
A semiconductor light emitting apparatus (4, 4') includes a semiconductor light emitting element (1) having a first electrode (11-1, 11-2, ..., 11-6, 11) and a second electrode (12); a substrate (2) having first and second wiring pattern layers (21, 22) electrically-connected to the first and second electrodes (11-1, 11-2, ..., 11-6, 11; 12), respectively; and multiple conductive bonding layer elements (40', 41', 42') provided between the first electrode (11-1, 11-2, ..., 11-6, 11) and the first wiring pattern layer (21) and/or between the second electrode (12) and the second wiring pattern layer (22). A method for manufacturing the same is also disclosed.