Discrete Barrier Members for Semiconductor Trench Planarization
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Solution Overview
Problem
The CMP process struggles to effectively planarize large size trenches in semiconductor structures, leading to suboptimal performance due to deformation of polishing pads and resulting concave-shaped barrier structures, which increase electromagnetic wave loss and hinder performance improvement.
Innovation Solution
A method involving the formation of discrete first and second openings in a dielectric structure, with first and second barrier members, where the second openings expose sidewall surfaces of the first barrier members, allowing for a barrier structure configuration that reduces electromagnetic wave loss and improves performance by preventing concave shapes during planarization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If CMP process is used to planarize large size trenches, then planarization is achieved, but the barrier structure becomes concave-shaped and performance deteriorates
Solution Approach 1:
The patent divides the continuous barrier layer into discrete barrier structures positioned at specific locations (e.g., at corners or along edges of the trench). This segmentation allows the barrier to maintain adequate thickness at critical locations without requiring complete planarization of the entire trench bottom, thereby avoiding the concave-shaped defect while maintaining electromagnetic wave shielding performance.
Solution Approach 2:
The patent applies barrier material selectively at specific locations within the trench rather than uniformly across the entire trench bottom. The barrier structures are concentrated at critical areas where electromagnetic wave reflection is most needed (such as corners and edges), allowing reduced barrier thickness or absence in non-critical areas, thus preventing the formation of concave-shaped barriers while maintaining overall performance.
2Manufacturing precision
If CMP process is used for planarization, then surface flatness is improved, but polishing pad deformation occurs and barrier thickness becomes insufficient
Solution Approach 1:
By segmenting the barrier into discrete structures at critical locations, the patent eliminates the need for complete planarization that would otherwise be required to maintain uniform barrier thickness. The CMP process can be stopped earlier, preserving barrier material thickness at critical locations while still achieving sufficient surface flatness for subsequent processing.
Solution Approach 2:
The patent applies the CMP process partially - only enough to achieve the minimum required surface flatness for subsequent lithography processes, rather than complete planarization. This partial action preserves adequate barrier material thickness while still providing sufficient planarity for pattern formation.
Data Source
AI summary
Semiconductor structures and fabrication methods are provided. The semiconductor structure includes a semiconductor substrate having a dielectric structure and having at least a first region; a plurality of first openings formed in the dielectric structure in the first region; a first barrier member formed in each of the plurality of the first openings; a plurality of second openings formed between adjacent first barrier members and with sidewall surfaces exposing sidewall surfaces of the first barrier members; and a second barrier member formed in each of the plurality second openings.