Discrete Buffer Memory for NVMe-over-RDMA Data Transfer

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Solution Overview

Problem

Conventional NVMe-over-RDMA approaches suffer from bottlenecks caused by server system memory, requiring special proprietary NVMe storage devices and limiting compatibility, while also increasing latency and dependency on server CPU and system memory.

Innovation Solution

A discrete buffer memory device with a PCIe bus interface and a controller that independently processes NVMe-over-RDMA commands and user data, reducing server host involvement by using a random access memory for submission and completion queues, and providing power failure recovery through a battery and non-volatile memory.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If RDMA protocol is used to transfer data from client system memory to server system memory, then data transfer capability is improved, but server system memory becomes a bottleneck

Engineering Contradiction:
Improvedata transfer capabilityVSAvoidserver system memory bottleneck
Core Design Contradiction:
SpeedVSProductivity

Solution Approach 1:

The patent extracts the buffer memory function from the server system memory and places it directly in the NVMe storage device. This allows data to be transferred from client system memory directly to the storage device's buffer memory, bypassing the server system memory bottleneck while maintaining RDMA transfer capabilities.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces a buffer memory within the NVMe storage device as an intermediary between the network interface and the storage medium. This intermediary buffer receives data directly via RDMA from client system memory and manages the transfer to storage, eliminating the need for server system memory to act as the intermediary.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If buffer memory is integrated in NVMe storage device controller, then server system memory bottleneck is reduced, but compatibility is limited due to proprietary requirements

Engineering Contradiction:
Improveserver system memory bottleneck reductionVSAvoidsystem compatibility
Core Design Contradiction:
ProductivityVSAdaptability or versatility

Solution Approach 1:

The patent implements a universal buffer memory architecture that can be integrated into standard NVMe storage devices without requiring proprietary modifications. The buffer memory works with conventional NVMe devices through standard interfaces, making the solution broadly compatible while still eliminating the server system memory bottleneck.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Ease of operation

If server CPU and system memory are involved in data transfer, then data transfer functionality is achieved, but latency increases

Engineering Contradiction:
Improvedata transfer functionalityVSAvoidtransfer latency
Core Design Contradiction:
Ease of operationVSLoss of time

Solution Approach 1:

The patent enables the NVMe storage device to serve itself by performing data transfer operations directly from the buffer memory to the storage medium without requiring server CPU intervention. The storage device autonomously manages the data transfer process, significantly reducing latency while maintaining full functionality.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The patent uses the buffer memory to preliminarily store incoming data before the storage device needs to write it to the storage medium. This preliminary action allows the storage device to retrieve data at its own pace without waiting for server CPU preparation, reducing transfer latency.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10423568B2Apparatus and method for transferring data and commands in a memory management environment
Publication Date: 2019.09.24 MICROSEMI SOLUTIONS US INC
  • US10423568B2 patent drawing
  • US10423568B2 patent drawing
  • US10423568B2 patent drawing

AI summary

A method and system for transferring NVMe data over a network comprises using a discrete buffer memory device to generate a write command from an NVMe-over-RDMA write command request, store the user data from a client host of the network, and send an interrupt signal to a NVMe storage device of the network. The NVMe storage device retrieves the write command from the discrete buffer memory device and performs a direct memory access transfer of the stored user data from the discrete buffer memory device to the NVMe storage device. The discrete buffer memory device comprises a controller and a random access memory for generating commands and storing the commands in a submission queue of the random access memory. The controller can clear commands from the submission queue based on completion commands received in a completion queue of the random access memory.