Discrete Charge Trapping Elements for 3D NAND
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Solution Overview
Problem
Three dimensionally stacked NAND flash memory devices with a charge trap layer face lateral charge migration issues, causing unwanted shifts in threshold voltage and read current, which affect data retention and storage reliability.
Innovation Solution
A vertical channel memory device is designed with discrete dielectric charge trapping elements in recessed regions on opposing sidewalls of conductive strips, isolated by vertical channel pillars and insulating structures, preventing lateral charge migration by separating charge trapping elements between adjacent stacks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a charge trap layer is shared between word lines in 3D NAND flash memory, then storage capacity is increased, but lateral charge migration occurs causing threshold voltage shifts and read current instability
Solution Approach 1:
The charge trap layer is segmented into discrete charge trapping elements that are laterally isolated from each other. This segmentation prevents charge migration between adjacent word lines while maintaining charge storage capability, thus resolving the contradiction between increased storage capacity and threshold voltage stability.
Solution Approach 2:
An insulating structure is introduced as an intermediary between discrete charge trapping elements on adjacent stacks. This insulating barrier prevents lateral charge migration while allowing the charge trap layer to function across multiple word lines, thereby maintaining both storage capacity and voltage stability.
2Reliability
If discrete charge trapping elements are isolated by vertical channel pillars and insulating structures, then lateral charge migration is prevented, but device complexity increases
Solution Approach 1:
The vertical channel pillars serve dual functions: they provide mechanical support and electrical isolation between stacks, while also acting as the insulating structures that prevent lateral charge migration. By merging these functions into a single structural element, the patent reduces overall device complexity while maintaining charge storage reliability.
Data Source
AI summary
A memory device includes a plurality of stacks of conductive strips alternating with insulating strips, the insulating strips having first and second sides, and the conductive strips having first sidewalls recessed relative to the first sides of the insulating strips which define first recessed regions in sides of the stacks. Vertical channel pillars are disposed between the stacks, the vertical channel pillars having first and second channel films disposed on adjacent stacks and a dielectric material between and contacting the first and second channel films. Data storage structures at cross points of the vertical channel pillars and the conductive strips include tunneling layers in contact with the vertical channel pillars, discrete charge trapping elements in the first recessed regions in contact with the tunneling layers and blocking layers between the discrete charge trapping elements and the first sidewalls of the conductive strips.