Discrete Discipline Verification for Digital Circuit Connectivity
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Solution Overview
Problem
Current methods for verifying power supply connectivity in complex chipsets with multiple supply sensitivities are inefficient, requiring substantial simulation time and resources, and often result in reduced functional coverage and increased costs.
Innovation Solution
Defining discrete properties or disciplines for each operating parameter of the circuit design, associating them with digital nets, and verifying connections based on compatibility without performing simulations, allowing for efficient verification of power supply connectivity across different voltage and clock domains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If transistor level verification using fastSPICE/fastMOS is performed, then verification accuracy is improved, but simulation time and computing resources increase substantially
Solution Approach 1:
The verification process is segmented into two distinct phases: a discrete property assignment phase that operates at the net level without simulation, and a compatibility verification phase that checks connections based on assigned properties. This segmentation allows accurate verification of power supply connectivity without requiring time-consuming transistor-level simulations.
Solution Approach 2:
Discrete properties are assigned to digital nets in advance during the design elaboration phase, before any simulation or connectivity verification is performed. This preliminary assignment of properties (such as supply voltage, clock frequency, and retention requirements) enables subsequent rapid verification of power supply connectivity without repeating time-consuming simulations.
2Ease of manufacture
If manual partitioning using stubs is performed, then verification costs are reduced, but functional coverage decreases and interdependencies between cells are ignored
Solution Approach 1:
The discrete property assignment mechanism serves multiple functions simultaneously: it assigns supply voltage information, clock frequency data, retention requirements, and other operating parameters to digital nets. This universal approach enables comprehensive verification of multiple supply domains without requiring separate verification processes for each function, thereby maintaining high functional coverage while reducing costs.
3Loss of time
If analog-behavioral models are used to speed up simulations, then simulation time is reduced, but functional coverage improves and calibration with SPICE netlist becomes difficult
Solution Approach 1:
The patent replaces the mechanical simulation process (which requires time-consuming SPICE netlist calibration) with a discrete property-based verification system. Instead of using analog-behavioral models that need calibration, the system assigns discrete properties to digital nets and verifies connectivity based on property compatibility, eliminating the calibration step entirely while maintaining verification accuracy.
4Adaptability or versatility
If digital blocks with different supply sensitivities are scattered across the chip, then design flexibility is improved, but verification complexity increases
Solution Approach 1:
The verification approach adds a new dimension of organization by assigning discrete properties to digital nets, which groups blocks by their supply sensitivity requirements rather than by physical location. This property-based dimension allows flexible scattering of blocks across the chip while simplifying verification, as the system verifies connectivity based on property compatibility rather than spatial proximity.
Data Source
AI summary
Connections between digital blocks and other circuit components, such as power supplies and clocks, are verified using a discrete property or object, such as a discrete discipline. A discrete discipline is defined for each value of an operating parameter, such as voltage or clock speed, that is used in a circuit design. Each discrete discipline is propagated throughout respective nets using bottom-up and/or top-down propagation. As a result, each digital net is associated with a power supply value through its corresponding discrete discipline. A determination is made whether two digital nets are connected to each other within the same digital island. If so, a determination is made whether the digital nets are compatible. If they have conflicting discrete disciplines, then they are not compatible and an error report or signal can be generated to identify the incompatibility and its location. Compatibility checks can disregard grounded digital nets. Verifications can be performed for both digital and mixed signal digital/analog designs without running simulations.