Discrete Gate Layouts for Higher-Density Semiconductor FETs
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Solution Overview
Problem
Conventional semiconductor designs face limitations in further miniaturization and efficient utilization of structural features, particularly in FETs, due to restrictive grid structures and fixed cell layouts, leading to inefficiencies in device density and performance.
Innovation Solution
The implementation of flexible gate cut processes to form discrete gate structures and separation regions, allowing for self-aligned patterning and non-rectangular transistor arrangements, combined with backside power distribution networks, enhances device flexibility and density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional grid structures and fixed cell layouts are used, then manufacturing simplicity is maintained, but device density and performance are limited
Solution Approach 1:
The gate structure is segmented into multiple discrete gate structures separated by gate separation regions. This segmentation allows independent control and flexible arrangement of transistor devices, enabling non-rectangular layouts and improved device density without compromising manufacturing feasibility through standardized process steps.
Solution Approach 2:
The invention transitions from conventional two-dimensional grid layouts to a more flexible spatial arrangement by introducing gate separation regions that enable non-rectangular transistor reservations. This dimensional flexibility allows optimization of device density in both planar and vertical directions.
2Reliability
If gate structures are continuously formed without separation, then manufacturing process is simplified, but device isolation and individual control are compromised
Solution Approach 1:
Gate separation regions are extracted between adjacent gate structures to provide electrical isolation and mechanical separation. This extraction enables individual control of each transistor device while maintaining a relatively simple manufacturing process through standard deposition and etching steps.
3Area of stationary object
If rectangular transistor arrangements are used, then layout simplicity is maintained, but space utilization efficiency is reduced
Solution Approach 1:
The invention employs asymmetric gate separation region configurations that allow non-rectangular transistor reservations. This asymmetry optimizes space utilization by adapting the layout to specific circuit requirements rather than forcing all devices into uniform rectangular arrangements, thereby improving chip area utilization.
Data Source
AI summary
A semiconductor device includes a set of transistor devices including respective discrete gate structures, a set of gate separation regions, where each discrete gate structure is disposed between a pair of the gate separation regions. The semiconductor device also includes a set of gate contacts, where each gate contact is connected to a corresponding one of the discrete gate structures.