Discrete Interconnect Substrate Layout for Package Warpage Control
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving high integration density and miniaturization while maintaining high performance and reliability, especially in large package sizes where warpage and board level reliability issues arise.
Innovation Solution
The implementation of a system on integrated substrate (SoIS) with multiple substrates attached, featuring a redistribution structure formed on a carrier substrate, interconnect structures mounted on the redistribution structure, and a molded underfill material used to encapsulate and support the interconnect structures, thereby reducing warpage and improving board level reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple substrates are attached to form a large system package, then integration density and functionality are improved, but warpage and board level reliability issues worsen
Solution Approach 1:
The patent divides the large system package into multiple smaller substrate units (first substrate, second substrate, etc.) that are separately managed and then interconnected. This segmentation allows each substrate to maintain dimensional stability while collectively achieving high integration density, thereby resolving the warpage issue in large packages.
Solution Approach 2:
The patent introduces an intermediary substrate or interconnect structure between the multiple substrates to facilitate electrical connection and mechanical support. This intermediary element helps distribute stresses and prevents warpage propagation, improving board level reliability while maintaining high functionality.
2Reliability
If full-sized interconnect substrates are fabricated, then electrical performance is maintained, but manufacturing costs increase
Solution Approach 1:
Instead of fabricating a single full-sized interconnect substrate, the patent segments the interconnection function across multiple smaller substrates. Each substrate can be manufactured using standard processes at lower cost, while the collective system achieves the required electrical performance through interconnection.
Solution Approach 2:
The patent applies interconnect structures only where needed between specific substrates rather than providing full coverage across a large substrate. This localized approach reduces material usage and manufacturing cost while maintaining electrical performance in critical areas.
3Area of stationary object
If package size is reduced for miniaturization, then portability is improved, but the number of input/output pads that can be integrated decreases
Solution Approach 1:
The patent transitions from a two-dimensional layout to a three-dimensional stacked configuration with multiple substrates arranged vertically. This dimensional change allows numerous input/output pads to be integrated in the vertical dimension while keeping the horizontal package footprint small, achieving both miniaturization and high I/O capacity.
Solution Approach 2:
The patent employs a nested arrangement where multiple substrates are stacked and interconnected, with each substrate containing input/output pads. This nesting enables high functional density within a compact package by utilizing vertical space efficiently.
Data Source
AI summary
A system substrate package, a system package, and methods of forming the same are described herein. The system substrate package includes an integrated substrate with multiple discrete interconnect structures. In embodiments the multiple discrete interconnect structures are placed and encapsulated and have a gap formed between the multiple discrete interconnect structures. The system substrate package reduces package warpage and mitigates board level reliability issues.