Digital Neural Processing with Discrete-Level Synapses
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Solution Overview
Problem
Neuromorphic processors face challenges with synapse weight training due to the need for analog or multi-level digital memory, which results in poor retention, large die area requirements, and excessive parallel interconnect wires, especially when implementing spike-timing-dependent plasticity (STDP) rules.
Innovation Solution
A digital neural processing unit with discrete-level synapses and probabilistic synapse weight training, where the synapse weight changes in discrete levels based on the time elapsed between spikes from post-synaptic and pre-synaptic neurons, using a probabilistic STDP approach that simplifies hardware implementation and reduces the number of bits required for weight representation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If analog memory is used for storing synaptic weights, then the neural processor can implement STDP rules, but the die area increases and retention capability deteriorates
Solution Approach 1:
The patent replaces analog memory systems with a digital neural processing unit that uses discrete-level synapses (2-3 levels) and probabilistic STDP rules. This substitution of analog with digital architecture eliminates the need for large analog memory arrays while maintaining STDP functionality through probabilistic weight updates based on spike timing differences.
Solution Approach 2:
The patent changes the parameter of synapse weight representation from continuous analog values to discrete levels (binary or ternary). This parameter transformation allows the system to achieve comparable learning performance with significantly reduced memory requirements, as discrete levels can be stored efficiently in digital memory without the area overhead of analog storage.
2Adaptability or versatility
If multi-level digital memory is used for storing synaptic weights, then the neural processor can implement STDP rules, but the number of parallel interconnect wires increases
Solution Approach 1:
The patent segments the synapse weight representation into discrete levels (2-3 levels per synapse) rather than using fine-grained multi-level representations. This segmentation reduces the number of bits required per synapse, thereby reducing the number of parallel interconnect wires needed to transport weight values during STDP operations.
Solution Approach 2:
The patent replaces complex multi-level digital memory systems with a simplified digital neural processing unit that uses probabilistic STDP rules and discrete synapse levels. This substitution reduces interconnect complexity by eliminating the need for high-precision weight storage and transmission pathways.
3Adaptability or versatility
If analog memory is used for storing synaptic weights, then the neural processor can implement STDP rules, but the retention capability is poor
Solution Approach 1:
The patent replaces analog memory with digital memory architecture, which inherently provides superior data retention characteristics. Digital memory stores synapse weights as discrete digital values that maintain their state indefinitely without the degradation issues inherent in analog storage, thereby solving the retention problem while preserving STDP functionality.
Data Source
AI summary
Certain embodiments of the present disclosure support implementation of a digital neural processor with discrete-level synapses and probabilistic synapse weight training.