Discrete-Time Linear Equalizer for PAM-4 Signal Integrity
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Solution Overview
Problem
Continuous-time analog front-ends (CT-AFEs) in high-speed serial data receivers face challenges in realizing circuit functions due to conflicting constraints of power, linearity, noise, and substrate area, especially with increasing data rates and decreasing power supply voltages, leading to non-linear compression and linear distortion, particularly in multi-level data formats like PAM-4 signaling.
Innovation Solution
Implementing a discrete-time analog front-end (DT-AFE) that includes a discrete-time linear equalizer (DTLE) and a discrete-time programmable gain amplifier (DT-PGA), which processes signals in the discrete-time domain, reducing ADC dynamic range requirements and mitigating inter-symbol interference through feed-forward equalization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If continuous-time analog front-end (CT-AFE) is used to terminate data channel and equalize received signal, then signal processing capability is provided, but power consumption increases and circuit implementation becomes difficult at high data rates with advanced CMOS technologies
Solution Approach 1:
The patent replaces the continuous-time analog front-end (CT-AFE) with a discrete-time analog front-end (DT-AFE). This substitution transforms the signal processing approach from continuous-time domain to discrete-time domain, enabling efficient operation at high data rates while reducing power consumption. The discrete-time architecture uses sampled signals and digital signal processing techniques instead of continuous analog processing, which resolves the contradiction between achieving high productivity and minimizing energy consumption.
2Productivity
If continuous-time analog front-end (CT-AFE) circuit functions are designed to handle high data rates, then data processing capability improves, but circuit complexity increases and implementation becomes increasingly difficult
Solution Approach 1:
The patent substitutes complex continuous-time analog circuitry with a discrete-time architecture that combines analog-to-digital conversion with digital signal processing. This replacement simplifies circuit implementation by using standard digital logic and processing techniques rather than requiring complex continuous-time analog circuit design, thereby reducing implementation difficulty while maintaining high data rate capability.
Solution Approach 2:
The patent segments the signal processing function into distinct stages: analog-to-digital conversion followed by discrete-time digital signal processing. This segmentation allows each stage to be optimized independently, with the ADC handling the analog-to-digital transition and subsequent digital circuits handling equalization and processing, thereby reducing overall circuit complexity compared to a monolithic continuous-time design.
3Use of energy by stationary object
If discrete-time analog front-end (DT-AFE) is implemented to reduce power consumption, then energy efficiency improves, but signal processing capability must be maintained
Solution Approach 1:
The patent employs discrete-time digital signal processing to replace power-consuming continuous-time analog processing while preserving signal processing capability. The discrete-time architecture processes sampled digital signals through digital equalizers and processors, maintaining equalization and signal recovery functions with lower power consumption characteristic of digital circuits compared to continuous-time analog circuits.
Data Source
AI summary
An apparatus comprises a discrete-time linear equalizer circuit. The discrete-time linear equalizer circuit comprises a sample and hold circuitry including multiple switched-capacitor circuits. The multiple switched-capacitor circuits include at least a switched-capacitor circuit of a pre-cursor tap, a switched-capacitor circuit of a cursor tap, and a switched-capacitor circuit of a post-cursor tap. A clock-driven switch circuitry is to switchably couple a capacitor of the switched-capacitor circuit of the pre-cursor tap to a signal input over a first time period, a capacitor of the switched-capacitor circuit of the cursor tap to the signal input over a second time period, and a capacitor of the switched-capacitor circuit of the post-cursor tap to the signal input over a third time period. The clock-driven switch circuitry is to switchably couple the capacitor of the switched-capacitor circuit of the cursor tap to an output, and the capacitors of the SHCs of the pre-cursor and post-cursor taps in a closed feedback loop with the capacitor of the switched-capacitor circuit of the cursor tap, over a fourth time period.