Discrete-Time Linear Equalizer Using Switched-Capacitor Taps
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Solution Overview
Problem
Continuous-time analog front-ends (CT-AFEs) in high-speed serial data receivers face challenges in realizing circuit functions due to conflicting constraints of power, linearity, noise, and substrate area, especially with increasing data rates and decreasing power supply voltages, and are compromised by process, voltage, and temperature variations, leading to non-linearity and linear distortion.
Innovation Solution
Implementing a discrete-time analog front-end (DT-AFE) that includes a discrete-time linear equalizer and programmable gain amplifier, which processes signals in the discrete-time domain, reducing ADC dynamic range requirements and mitigating inter-symbol interference through feed-forward equalization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If continuous-time analog front-end (CT-AFE) is used to terminate data channel and equalize received signal, then signal equalization function is achieved, but power consumption increases and circuit complexity increases due to conflicting constraints of power, linearity, noise, and substrate area
Solution Approach 1:
The patent replaces the continuous-time analog front-end (CT-AFE) with a discrete-time analog front-end (DT-AFE). This substitution fundamentally changes the operational domain from continuous-time to discrete-time, enabling the system to achieve signal equalization while reducing power consumption and circuit complexity. The discrete-time approach uses switched-capacitor circuits that operate in periodic intervals rather than continuously, thereby reducing power consumption while maintaining equalization performance.
Solution Approach 2:
The patent changes the operational parameter from continuous-time to discrete-time domain. By transforming the equalization process from continuous operation to periodic discrete operation, the system achieves the same signal processing function with reduced power consumption. The discrete-time equalizer uses time-multiplexed switched-capacitor circuits that perform equalization operations at specific sampling instants rather than continuously, thereby reducing overall power consumption.
2Speed
If continuous-time analog front-end (CT-AFE) is used with increasing data rates and decreasing power supply voltages, then high-speed data reception is enabled, but circuit functions become increasingly difficult to realize and performance degrades due to process, voltage, and temperature variations
Solution Approach 1:
The patent replaces the continuous-time analog front-end with a discrete-time analog front-end that operates in the discrete-time domain. This substitution makes the circuit functions more robust against process, voltage, and temperature variations. The discrete-time equalizer uses switched-capacitor circuits with well-defined sampling instants, making the circuit behavior more predictable and less sensitive to PVT variations compared to continuous-time circuits operating at high data rates with decreasing supply voltages.
3Use of energy by moving object
If discrete-time analog front-end (DT-AFE) is implemented to process signals in discrete-time domain, then power consumption is reduced and ADC dynamic range requirements are reduced, but device complexity changes from continuous-time to discrete-time architecture
Solution Approach 1:
The patent implements periodic action through time-multiplexed switched-capacitor circuits that operate in discrete periodic intervals. The discrete-time equalizer uses clock-driven switching to perform equalization operations at specific sampling instants rather than continuously. This periodic operation reduces power consumption while the time-multiplexing approach efficiently manages the circuit resources, making the discrete-time architecture practical despite the initial appearance of increased complexity.
4Reliability
If discrete-time linear equalizer is used to mitigate inter-symbol interference through feed-forward equalization, then signal quality is improved, but circuit complexity increases due to multiple switched-capacitor circuits and clock-driven switching
Solution Approach 1:
The patent merges multiple equalization functions into a unified discrete-time linear equalizer structure. The time-multiplexed switched-capacitor circuits perform multiple equalization operations sequentially within a periodic framework. By combining the equalization functions and using shared clock-driven switching infrastructure, the circuit achieves improved signal quality through feed-forward equalization while managing the complexity through systematic integration rather than separate independent circuits.
Data Source
AI summary
An apparatus comprises a discrete-time linear equalizer circuit. The discrete-time linear equalizer circuit comprises a sample and hold circuitry including multiple switched-capacitor circuits. The multiple switched-capacitor circuits include at least a switched-capacitor circuit of a pre-cursor tap, a switched-capacitor circuit of a cursor tap, and a switched-capacitor circuit of a post-cursor tap. A clock-driven switch circuitry is to switchably couple a capacitor of the switched-capacitor circuit of the pre-cursor tap to a signal input over a first time period, a capacitor of the switched-capacitor circuit of the cursor tap to the signal input over a second time period, and a capacitor of the switched-capacitor circuit of the post-cursor tap to the signal input over a third time period. The clock-driven switch circuitry is to switchably couple the capacitor of the switched-capacitor circuit of the cursor tap to an output, and the capacitors of the SHCs of the pre-cursor and post-cursor taps in a closed feedback loop with the capacitor of the switched-capacitor circuit of the cursor tap, over a fourth time period.