Discrete-Time Phase-Lock Loop for Variable Frequency Ratios
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Solution Overview
Problem
Existing phase-lock techniques, such as continuous-time phase-lock loops (CTPLLs), are limited by fixed integer multiplication factors, restricting frequency diversity and increasing circuit complexity when attempting to achieve high frequency accuracy and stability, particularly in mobile instruments.
Innovation Solution
A discrete-time phase-lock loop (DTPLL) with a digital signal processor (DSP) and reduced analog hardware, utilizing a digital-to-analog converter, oscillator, loop controller state machine, phase detector, divider, and loop filter to provide a clock signal and control effort, allowing for variable frequency ratios and reduced complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a continuous-time phase-lock loop (CTPLL) uses a fixed integer multiplication factor R, then the circuit complexity is simplified, but frequency diversity is eliminated and the reference frequency is restricted to integer sub-multiples of the output frequency
Solution Approach 1:
The patent implements a discrete-time phase-lock loop where the multiplication factor R can be dynamically changed during operation. The system transitions from a fixed integer multiplier to a variable multiplier that can be adjusted based on frequency requirements, enabling frequency diversity while maintaining a relatively simple circuit structure through digital control mechanisms.
Solution Approach 2:
The invention changes the fundamental parameter of the multiplication factor from a fixed integer to a variable parameter that can be adjusted. By allowing R to change dynamically and implementing fractional division capabilities, the system achieves arbitrary frequency ratios between the reference and output frequencies without requiring complex mixed-signal circuitry.
2Adaptability or versatility
If a CTPLL allows variable multiplication factor R to achieve frequency diversity, then frequency flexibility is improved, but the circuit complexity increases significantly requiring mixed signal technologies with higher power consumption and board space
Solution Approach 1:
The patent replaces complex analog/mixed-signal circuitry with a digital implementation. By using a discrete-time architecture with digital signal processing, counters, and programmable logic, the system achieves variable frequency multiplication without requiring complex mixed-signal technologies, thereby reducing power consumption and board space while maintaining frequency diversity capabilities.
Solution Approach 2:
The invention uses periodic sampling and discrete-time processing to achieve frequency synthesis. By operating in discrete time domains with periodic updates of the multiplication factor and using digital counters synchronized to the reference frequency, the system achieves frequency diversity through software-programmable control rather than complex analog circuitry.
3Measurement precision
If a CTPLL uses a fractional divider for R to achieve arbitrary frequency ratios, then frequency accuracy is improved, but the circuit complexity and power consumption increase significantly
Solution Approach 1:
The patent implements fractional division using digital logic and software algorithms rather than complex analog fractional dividers. The discrete-time architecture allows for precise frequency control through digital counters and programmable logic that can achieve arbitrary frequency ratios with high accuracy while consuming less power and occupying less board space than traditional mixed-signal implementations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The DTPLL achieves phase-locking with reduced circuit complexity and power consumption, enabling frequency diversity while maintaining high frequency accuracy and stability, suitable for applications in measurement and communication devices.
Implementation Method 1
an analog section comprising a digital-to-analog converter (DAC) and an oscillator
Implementation Method 2
a phase detector; a counter, operative to receive clock signals from the oscillator and to provide a count value to the phase detector
Implementation Method 3
a loop filter operative to provide a control effort value based on an output from the phase detector
Implementation Method 4
an oscillator, operative to provide a clock signal based on an input from the DAC
Data Source
AI summary
A discrete-time phase lock loop (DTPLL) includes an analog section comprising a digital-to-analog converter (DAC) and an oscillator, operative to provide a clock signal based on an input from the DAC. The DTPLL also includes a digital signal processor (DSP). The DSP includes a loop controller state machine; a phase detector; a counter, operative to receive clock signals from the oscillator and to provide a count value to the phase detector; a divider, operative to receive a reference signal and to provide a reference pulse output to the phase detector; and a loop filter operative to provide a control effort value based on an output from the phase detector. Based on the phase error value, an output of the oscillator is changed to reduce the phase error to a steady state value.