Discrete-Time Sampling Calibration for Incomplete Settling
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Solution Overview
Problem
Existing discrete-time circuits with incomplete settling parameters result in gain errors and non-ideal conditions, which are not adequately corrected by current dither-based calibration techniques, and the sampling point is often not at the optimum point of the output waveform, leading to degraded signal-to-noise ratio and increased sensitivity to process, voltage, and temperature variations.
Innovation Solution
A method for adjusting the sampling time based on amplitude differences, using a variable delay clock and gain estimator to dynamically calibrate the sampling instant, accounting for process, voltage, and temperature changes, and incorporating a dither term to maintain convergence.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If dither-based calibration techniques are used to correct gain error, then gain error correction is achieved, but other effects caused by incomplete settling are not corrected and sampling point is not at optimum
Solution Approach 1:
The patent implements a feedback mechanism where the actual sampling point is detected by comparing the sampled value with the expected value, and the timing offset is adjusted based on the difference. This closed-loop feedback allows the system to automatically correct not only gain error but also other settling-related effects by continuously adapting the sampling timing to achieve optimal performance.
Solution Approach 2:
The patent changes the sampling timing parameter dynamically based on detected settling conditions. By adjusting the sampling point in time based on the actual waveform characteristics and settling behavior, the system optimizes performance across multiple parameters including gain accuracy, signal-to-noise ratio, and distortion, rather than relying on fixed calibration methods.
2Productivity
If sampling rate is increased to achieve high sample rates, then productivity is improved, but incomplete settling occurs resulting in gain error and non-ideal conditions
Solution Approach 1:
The patent makes the sampling timing dynamic by detecting the actual settling state of the amplifier output in real-time and adjusting the sampling point accordingly. This dynamic adaptation allows the system to operate at high sampling rates while maintaining accurate measurements, as the sampling instant automatically adapts to the actual waveform settling behavior rather than using a fixed timing scheme.
Solution Approach 2:
The patent replaces traditional fixed timing mechanisms with a detection-based timing system. Instead of relying on predetermined settling times or fixed sampling clocks, the system uses digital signal processing to detect the actual sampling point and adjust timing accordingly, substituting mechanical timing constraints with flexible digital control.
3Device complexity
If fixed sampling time is used, then device complexity is reduced, but sampling point is not at optimum leading to degraded signal-to-noise ratio
Solution Approach 1:
The system performs self-calibration by automatically detecting its own sampling point and adjusting timing without external intervention. The feedback mechanism allows the system to self-optimize the sampling instant based on actual waveform characteristics, achieving high signal-to-noise ratio performance without requiring complex external timing control systems or manual calibration procedures.
Data Source
AI summary
Aspects of the present disclosure include methods for operating discrete time circuits. A method in accordance with an aspect of the present disclosure may comprise sampling a first amplitude of a signal at a first time, sampling a second amplitude of the signal at a second time, comparing the first amplitude to the second amplitude, and adjusting a sampling time of the signal based at least in part on a difference between the first amplitude and the second amplitude.