Disk Array Cache Memory Segmentation for Failure Isolation

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Solution Overview

Problem

Conventional disk array apparatuses experience performance degradation and path switching issues when a failure occurs in a cache memory, as they require taking over entire I/O processing to another system, leading to load clustering and inability to continue I/O processing without redundant path configurations.

Innovation Solution

The disk array apparatus implements a dual cache memory system where only the failed memory area is closed and reallocated to another memory area within the same cache, allowing I/O processing to continue without transferring the entire load to another system, utilizing logical memory area management and reallocation based on load and connection states.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the entire I/O processing is taken over to another I/O processing controller when a cache memory failure occurs, then the system reliability is improved, but the load clustering causes performance degradation

Engineering Contradiction:
Improvesystem reliabilityVSAvoidperformance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The cache memory is divided into multiple independent memory areas, allowing selective closure of only the failed memory area rather than the entire cache memory. This segmentation enables continued operation of unaffected memory areas, preventing load clustering on alternative controllers while maintaining system reliability.

Inventive Principle:
Principle #1Segmentation

2Reliability

If the I/O processing controller with cache memory failure is closed, then the failure impact is isolated, but the entire I/O processing must be transferred causing performance degradation

Engineering Contradiction:
Improvefailure isolationVSAvoidperformance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The cache memory is segmented into multiple independent memory areas, enabling isolation of only the failed memory area while keeping the rest of the cache memory operational. This prevents unnecessary transfer of entire I/O processing to alternative controllers.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Instead of closing the entire I/O processing controller or taking over complete I/O processing, only the specific failed memory area is closed and reallocated. This partial action maintains system performance by keeping unaffected resources operational.

Inventive Principle:
Principle #16Partial or excessive action

3Device complexity

If redundant path configuration is not provided, then the system complexity is reduced, but I/O processing cannot be taken over when failure occurs

Engineering Contradiction:
Improvesystem complexityVSAvoidfailover capability
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The cache memory is divided into multiple independent memory areas with reallocation capability. This internal segmentation provides failover capability without requiring external redundant path configurations, reducing system complexity while maintaining reliability.

Inventive Principle:
Principle #1Segmentation

4Reliability

If the entire cache memory is closed due to partial failure, then data integrity is ensured, but the available memory capacity is reduced

Engineering Contradiction:
Improvedata integrityVSAvoidmemory capacity
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The cache memory is segmented into multiple independent memory areas, allowing the system to ensure data integrity in affected areas by closing only those specific areas while maintaining operational status and capacity of unaffected areas.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

When a memory area fails, it is closed and its functionality is recovered by reallocating it to a different memory area within the same cache memory, thereby preserving total memory capacity while ensuring data integrity.

Inventive Principle:
Principle #34Discarding and recovering

Data Source

PatentUS7774640B2Disk array apparatus
Publication Date: 2010.08.10 RAKUTEN GROUP INC
  • US7774640B2 patent drawing
  • US7774640B2 patent drawing
  • US7774640B2 patent drawing

AI summary

A disk array apparatus where, when a failure occurs at a part of a cache memory, a memory area of an I/O processing controller other than the memory area where the failure has occurred is utilized without taking over the whole I/O processing to an I/O processing controller of other system is provided, so that influence of performance degradation can be minimized. In a disk array apparatus including dual cache memories, when a failure occurs at a part of the cache memory, only a memory area where the failure has occurred is closed, and reallocation thereof to another memory area of the same cache memory is conducted to continue an I/O processing.