Magnetic Disk Drive Write Circuit Switching Speed
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Solution Overview
Problem
Magnetic disk drives face challenges in efficiently writing data due to the slow reaction of inductive loads to changes in write current, leading to delays in generating magnetic fields for data storage, and issues with parasitic capacitance and timing problems in switching logic states.
Innovation Solution
A system that includes a bias current generator and an overshoot current generator, which activate output transistors to generate write currents through a write head, with the overshoot current increasing the write current during an overshoot phase and reducing parasitic capacitance by controlling bias voltages, allowing for active switching and rapid data transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional switching logic is used to control write current, then device complexity is reduced, but switching speed is slow due to inductive load reaction time
Solution Approach 1:
The patent applies preliminary action by pre-charging capacitor nodes (e.g., node 106, 108) to specific voltage levels before switching occurs. The bias current generators (120, 122) continuously charge capacitors (105, 115) so that when switches (Q1, Q2) are activated, the write current transitions occur rapidly without waiting for inductive load response. This pre-positioning of electrical energy enables faster switching speeds while managing the complexity through structured circuit design.
2Speed
If inductive load is used in write head, then magnetic field generation is achieved, but response time to current changes is slow
Solution Approach 1:
The patent employs periodic action through pulsed write current signals that alternately activate different output transistors (Q1, Q2) to generate magnetic fields in alternating directions. The pulse generator (12) creates periodic switching patterns that drive the inductive load (write head) to write binary data. This periodic switching maintains reliable magnetic field generation while improving response time by using controlled current pulses rather than continuous current, allowing the inductive load to respond more quickly to each transition.
3Loss of time
If parasitic capacitance is present in switching circuit, then circuit implementation is simplified, but timing precision deteriorates
Solution Approach 1:
The patent converts the harmful effect of parasitic capacitance into a beneficial element by deliberately adding compensation capacitors (105, 115) to the circuit. These capacitors are specifically sized to offset the timing delays caused by parasitic capacitance in the switching transistors and interconnects. The bias current generators (120, 122) charge these compensation capacitors during the write operation, and their discharge characteristics are designed to counteract the unwanted timing delays, thereby improving timing precision while accepting the added circuit complexity as a necessary trade-off.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables high data rates, such as 4 gigabits per second, by actively switching the write current and reducing transistor deactivation delays, while mitigating parasitic capacitance and timing issues, resulting in efficient data storage with rapid switching times.
Implementation Method 1
The magnetic field is applied based on providing a current through an inductive load that is located in the write head of the disk drive
Data Source
AI summary
One embodiment of the invention includes a system for writing data onto a magnetic disk. An output driver provides a first write current through a first output transistor in a first state and provides a second write current through a second output transistor in a second state. The first and second write currents can be provided to a disk write head to store opposing binary values, respectively. A bias current generator switches a first bias current between an intermediate voltage node in the second state and a first control node in the first state, and switches a second bias current between the intermediate voltage node in the first state and a second control node in the second state. The first and second bias currents can be provided to set a bias voltage at the first and second control nodes to bias the first and second output transistors, respectively.