Disk-ROM Memory System for Power-Efficient Server Main Memory
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Solution Overview
Problem
Traditional non-volatile memory integrated circuits are too slow for main memory in server computer systems, but recent improvements in NOR FLASH EEPROM have reduced read access times, and non-volatile memory conserves power without significant read access time penalties, while cache memory improves access times by maintaining data coherence.
Innovation Solution
A disk-read-only-memory (disk-ROM) system that straddles the hardware layers between main memory and block-accessible storage, allowing random read and write access at the granularity of bytes or blocks, bypassing traditional file system operations for efficient data access and coherence management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If traditional non-volatile memory integrated circuits are used, then power consumption is reduced, but read access time becomes too slow for main memory applications
Solution Approach 1:
The memory system is segmented into multiple memory modules, each with its own cache memory. This allows parallel access to different memory segments, effectively increasing the overall read access speed while maintaining the power-saving benefits of non-volatile memory. The segmentation enables the system to bypass the slow read access of non-volatile memory for frequently accessed data by storing it in faster cache memory modules.
Solution Approach 2:
Cache memory is introduced as an intermediary between the processor and non-volatile memory. This intermediary layer provides fast read access to frequently accessed data, eliminating the need for slow direct reads from non-volatile memory. The cache memory acts as a buffer that mediates between the high-speed processor and the low-speed non-volatile memory, resolving the speed contradiction.
2Speed
If cache memory is used to improve access times, then read and write access times are improved, but system complexity increases due to cache coherency protocols
Solution Approach 1:
The cache coherency problem is segmented by assigning dedicated cache memory to each memory module and processor complex. This segmentation isolates cache coherency management to smaller, manageable units rather than requiring system-wide coherency protocols. Each memory module's cache operates semi-independently, reducing the overall system complexity while maintaining fast access times.
3Use of energy by stationary object
If non-volatile memory is used instead of DRAM, then power consumption is conserved, but read access time increases significantly
Solution Approach 1:
Data is preliminarily loaded from non-volatile memory into cache memory before it is needed for processing. This preliminary action ensures that when the processor needs data, it is already available in the fast cache memory, eliminating the time penalty of reading from non-volatile memory. The system proactively manages data movement to prevent slow access rather than reacting to it.
Data Source
AI summary
In one embodiment of the invention, a memory apparatus is disclosed. The memory apparatus includes a memory array, a block read/write controller, and a random access read memory controller. The memory array is block read/write accessible and random read accessible. The block read/write controller is coupled between the memory array and an external interconnect. The block read/write controller performs block read/write operations upon the memory array to access blocks of consecutive memory locations therein. The random access read memory controller is coupled between the memory array and the external interconnect in parallel with the block read/write access controller. The random access read memory controller performs random read memory operations upon the memory array to access random memory locations therein.