Dislocation Nucleation Layer for NMOS Tensile Strain

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Solution Overview

Problem

Existing methods for improving carrier mobility in CMOS transistors, such as those described in US20130146895A1, face challenges in achieving differential strain requirements for NMOS and PMOS channels, with existing strain mechanisms potentially degrading channel performance.

Innovation Solution

The formation of a dislocation nucleation layer with a silicon germanium material in the source/drain regions, which induces a tensile strain in the channel region by propagating dislocations and overcoming compressive stress, using epitaxial growth and doping techniques to optimize strain transfer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If existing strain mechanisms are used to improve carrier mobility, then carrier mobility is improved, but channel performance degrades

Engineering Contradiction:
Improvecarrier mobilityVSAvoidchannel performance
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent divides the source/drain structure into multiple segments: a first source/drain region, a second source/drain region, and a channel region. By segmenting the structure and applying different strain conditions to different segments, the patent achieves tensile strain in the channel for improved carrier mobility while preventing performance degradation through proper structural design and material selection in each segment.

Inventive Principle:
Principle #1Segmentation

2Speed

If tensile strain is applied to NMOS channel to improve mobility, then carrier mobility is improved, but differential strain requirements for PMOS cannot be met

Engineering Contradiction:
Improvecarrier mobilityVSAvoiddifferential strain requirements
Core Design Contradiction:
SpeedVSAdaptability or versatility

Solution Approach 1:

The patent applies different material compositions and strain conditions to different local regions. The first source/drain region uses a different material composition than the second source/drain region, creating local quality differences that enable tensile strain in the NMOS channel while allowing compressive strain in the PMOS channel, thus meeting differential strain requirements for different transistor types.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent introduces asymmetry in the source/drain structure by using different materials and configurations for the first and second source/drain regions. This asymmetric design enables the structure to provide opposite strain types (tensile for NMOS, compressive for PMOS) to different transistor portions, satisfying the asymmetric strain requirements of complementary CMOS devices.

Inventive Principle:
Principle #4Asymmetry

3Stress or pressure

If buffer layers are used to induce strain, then strain transfer is achieved, but manufacturing complexity increases

Engineering Contradiction:
Improvestrain transferVSAvoidbuffer layer structure
Core Design Contradiction:
Stress or pressureVSDevice complexity

Solution Approach 1:

The patent extracts and eliminates the buffer layer from the traditional strain-induced transistor structure. Instead of using a separate buffer layer to induce strain, the patent directly forms the source/drain regions with appropriate material compositions that inherently provide the required strain, thereby simplifying the device structure and reducing manufacturing complexity while maintaining effective strain transfer.

Inventive Principle:
Principle #2Taking out (Extraction)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances carrier mobility by effectively inducing a tensile strain in the NMOS channel region while avoiding performance degradation associated with buffer layers, thereby improving transistor performance.

Implementation Method 1

multiple dislocations are formed in the silicon germanium material, and then forming a source/drain material on the thin silicon germanium material, wherein the dislocations induce source/drain dislocations throughout the source/drain material

Methodology Applied
Scientific EffectDislocation propagation: Deformation

Implementation Method 2

forming a silicon germanium material on source/drain openings

Methodology Applied
Scientific EffectEpitaxial growth: Epitaxy

Data Source

PatentEP3050090B1Methods of forming dislocation enhanced strain in NMOS structures
Publication Date: 2023.08.09 DAEDALUS PRIME LLC
  • EP3050090B1 patent drawingFigure 1a~1b
  • EP3050090B1 patent drawingFigure 1c~1d
  • EP3050090B1 patent drawingFigure 1e~2

AI summary

Methods of forming a strained channel device utilizing dislocations disposed in source/drain structures are described. Those methods and structures may include forming a thin silicon germanium material in a source/drain opening of a device comprising silicon, wherein multiple dislocations are formed in the silicon germanium material. A source/drain material may be formed on the thin silicon germanium material, wherein the dislocations induce a tensile strain in a channel region of the device.