Displaced TSV Stacking Without RDL for Higher-Yield Interconnects
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Solution Overview
Problem
The manufacturing process of Through-Silicon Vias (TSVs) using Re-Distribution Layers (RDLs is complex, time-consuming, and costly, resulting in low yield.
Innovation Solution
A through-silicon via interconnection structure and method that involves stacking upper substrate structures with TSVs and connecting wires to connect circuits without using RDL, utilizing displacement marks for accurate alignment and reducing the need for photolithography.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If Re-Distribution Layer (RDL) is used to achieve TSV displacement, then interconnection can be achieved, but manufacturing process becomes complicated and fabrication time increases
Solution Approach 1:
The patent extracts and eliminates the Re-Distribution Layer (RDL) from the TSV interconnection structure. By removing the RDL component entirely and using direct TSV-to-TSV alignment through displacement marks, the manufacturing process is simplified and fabrication time is reduced while maintaining the ability to achieve proper TSV displacement and connection.
2Ease of manufacture
If Re-Distribution Layer (RDL) is used for TSV displacement, then interconnection is achieved, but cost increases and yield decreases
Solution Approach 1:
The patent removes the RDL layer to reduce manufacturing cost and simplify the process. By using direct TSV alignment with displacement marks, the number of fabrication steps is reduced, which lowers cost and improves yield by minimizing process variations and potential failure points associated with additional layers.
Solution Approach 2:
The patent uses displacement marks that are copied or replicated across substrate structures to enable precise alignment. These marks serve as reference patterns that can be reproduced consistently, ensuring accurate TSV positioning without requiring complex RDL routing, thereby improving yield and reducing cost.
3Productivity
If multiple upper substrate structures are stacked with displacement, then circuit connection efficiency is improved, but alignment precision requirement increases
Solution Approach 1:
The patent implements displacement marks on substrate structures before the stacking process. These pre-formed marks serve as alignment references that guide the stacking operation, allowing multiple substrate structures to be accurately positioned and connected without requiring high precision during the actual stacking process, thus improving productivity while managing precision requirements.
Solution Approach 2:
The displacement marks act as intermediary elements between the substrate structures during stacking. These marks provide a reference system that mediates the alignment process, enabling accurate positioning of TSVs across multiple stacked structures without requiring direct high-precision alignment between all components, thereby facilitating efficient multi-layer connection.
Data Source
AI summary
The present disclosure relates to semiconductor technology and provides a TSV interconnection structure and a method for fabricating same. The TSV interconnection structure may include a plurality of upper substrate structures, wherein each of the plurality of upper substrate structures is provided with a plurality of TSVs, each of the plurality of upper substrate structures is stacked on and displaced from adjacent upper substrate structures, and at least some of the TSVs of each of the plurality of upper substrate structure are connected with corresponding TSVs of the adjacent upper substrate structures; and connecting wires disposed in the plurality of TSVs and configured to connect corresponding circuits on the plurality of upper substrate structures. The present disclosure utilizes a displacement arrangement between the upper substrate structures, so that the TSVs can be displaced and connected without using RDL for a better yield, shorter the fabrication time, and low costs.