Display Wiring Layout With 3D Interconnects to Reduce Dead Space
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Solution Overview
Problem
Conventional display apparatuses have a large area of dead space due to the placement of drivers and other components, which reduces the effective display area and affects image quality.
Innovation Solution
The display apparatus incorporates a novel layout with multiple semiconductor layers, gate layers, and connecting electrode layers, including polysilicon and oxide semiconductor materials, to optimize the arrangement of transistors and wiring, reducing the dead space area while maintaining high image quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If drivers and other components are placed in a peripheral area, then the display apparatus can control luminance of each pixel, but the dead space area becomes excessively large
Solution Approach 1:
The patent transitions from a planar peripheral arrangement to a multi-layered three-dimensional structure. Connection wirings are distributed across multiple layers (first, second, and third connecting electrode layers) with vertical connection wirings extending in a second direction to intersect horizontal connection wirings. This vertical stacking enables compact routing of data signals from the peripheral driver to pixels in the display area, significantly reducing the horizontal dead space while preserving full luminance control functionality.
Solution Approach 2:
The patent implements a nested hierarchical structure where connection wirings are organized in concentric layers. The first connecting electrode layer contains horizontal connection wirings, the second layer contains additional horizontal connection wirings, and the third layer contains vertical connection wirings that intersect and connect to both horizontal layers. This nested arrangement allows efficient signal routing within a compact footprint, minimizing the peripheral dead space while maintaining complete control over pixel luminance.
2Area of stationary object
If multiple connecting electrode layers are used to reduce dead space, then the wiring complexity increases
Solution Approach 1:
The patent divides the connection wiring system into three distinct functional layers: the first connecting electrode layer for initial horizontal signal distribution, the second connecting electrode layer for additional horizontal routing, and the third connecting electrode layer for vertical signal transfer. Each layer is independently patterned and optimized for its specific routing function, which simplifies the manufacturing process and reduces overall complexity compared to attempting to route all connections in a single complex layer.
Data Source
AI summary
A display apparatus includes a first semiconductor layer disposed on a substrate; a first gate layer disposed on the first semiconductor layer, the first gate layer including a driving gate electrode; a second gate layer disposed on the first gate layer, the second gate layer including a capacitor upper electrode; a first connecting electrode layer disposed on the second gate layer, the first connecting electrode layer including a transfer wiring; a second connecting electrode layer disposed on the first connecting electrode layer, the second connecting electrode layer including a horizontal connection wiring extending in a first direction; and a third connecting electrode layer disposed on the second connecting electrode layer, the third connecting electrode layer including a vertical connection wiring extending in a second direction that intersects the first direction.