Digital Display ADC Sampling Clock and Phase Synchronization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing digital display devices face challenges in accurately determining the sampling frequency and phase for analog-to-digital conversion, leading to impaired image quality due to noisy clocks, imprecise methods, and reliance on manual adjustments or costly hardware.
Innovation Solution
A digital display device with a phase-locked loop and programmable frequency divider, coupled with a sampling phase control circuit that uses a function minimization algorithm to select the optimal sampling phase, ensuring high-quality image reproduction by accurately determining the sampling frequency and phase.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a fixed dividing ratio is used in the frequency divider, then the circuit is simple, but the sampling frequency cannot be accurately adjusted to match the pixel clock frequency
Solution Approach 1:
The patent implements a dynamic frequency divider that can adjust its dividing ratio based on detected pixel clock frequency. The system initially uses a fixed divider with a predetermined ratio, detects the actual pixel clock frequency, then dynamically reconfigures the dividing ratio to achieve accurate sampling frequency matching. This resolves the contradiction by transitioning from a static to a dynamic system.
Solution Approach 2:
The patent changes the parameter of the frequency divider from a fixed dividing ratio to a variable dividing ratio that can be adjusted based on detected frequency information. The system detects the pixel clock frequency and accordingly adjusts the dividing ratio parameter to optimize sampling accuracy, resolving the contradiction between simplicity and precision.
2Measurement precision
If manual adjustment is used for sampling phase, then the device complexity is reduced, but the image quality and measurement precision deteriorate
Solution Approach 1:
The patent implements a self-adjusting phase control system that automatically detects and corrects sampling phase errors without requiring manual intervention. The system uses detected frequency information to automatically configure the phase controller, achieving high precision while minimizing the need for complex manual control interfaces.
Solution Approach 2:
The patent employs a feedback mechanism where the detected pixel clock frequency is fed back to automatically adjust the sampling phase configuration. This closed-loop approach ensures optimal phase alignment is achieved automatically, resolving the contradiction between automation complexity and measurement precision.
3Reliability
If the dividing ratio is not adjusted based on pixel clock frequency, then the device complexity is reduced, but the sampling frequency accuracy deteriorates
Solution Approach 1:
The patent performs preliminary frequency detection and dividing ratio configuration before actual image display begins. The system detects the pixel clock frequency and configures the optimal dividing ratio in advance, ensuring reliable image quality from the start without requiring complex real-time adjustment mechanisms during operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables high-quality image reproduction without manual adjustments and reduces the need for costly hardware, providing a reliable and efficient method for determining the correct sampling frequency and phase for digital display devices.
Implementation Method 1
The sampling clock is synchronized to the pixel clock by a phase-locked loop which ensures that the sampling frequency is an integer multiple of the pixel clock frequency.
Implementation Method 2
analog-to-digital conversion, identifying the correct sampling frequency for the ADCs is essential since even a small error in sampling frequency can impair the resulting displayed images
Data Source
AI summary
A method and apparatus for a digital video display. A digital display device receives an analog signal representing an image formed of pixels in video lines and a signal containing a synchronization waveform for the image. An analog-to-digital converter (ADC) receives the analog signal and converts it to a sampled digital waveform. A phase-locked loop including a programmable frequency divider controls the sampling time for the ADC. The programmable frequency divider is controlled by a dividing-ratio algorithm that selects a dividing ratio, measures the number of pixels in a video line using the dividing ratio, and recomputes the dividing ratio by multiplying the selected dividing ratio by the expected number of pixels in a video line and dividing by the measured number of pixels. The sampling phase for the ADC is selected by a sampling-phase control algorithm that minimizes a function representative of the flatness of the sampled digital waveform.