Multi-Stage Display Amplifier With Dynamic Current Boosting
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Solution Overview
Problem
Existing display apparatuses, particularly high-resolution small organic light emitting display devices, face challenges in minimizing pixel driving time and power consumption due to limitations in current amplifier circuits.
Innovation Solution
The proposed solution involves an amplifier circuit with a specific configuration including multiple stages and boosting circuits, utilizing PMOS and NMOS transistors to manage current flow and voltage amplification, which enables rapid voltage changes and reduced driving time, thereby minimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If conventional amplifier circuits are used in high-resolution small organic light emitting display devices, then the display device can be manufactured with wafer-based semiconductor process, but the pixel driving time cannot be minimized due to limited current flow speed
Solution Approach 1:
The amplifier circuit is divided into multiple stages (first stage, second stage, third stage) with each stage performing specific functions. The first stage handles input signal amplification, the second stage provides intermediate amplification with pull-up and pull-down nodes, and the third stage outputs the final amplified signal. This segmentation allows optimization of current flow at each stage to minimize pixel driving time.
Solution Approach 2:
The amplifier circuit incorporates dynamic current boosting capability through the first and second boosting circuits. These boosting circuits can instantaneously increase current flow during rising and falling periods based on the amplification direction, making the circuit adaptive to different operating conditions and minimizing driving time dynamically.
2Loss of time
If higher current flow is used to reduce pixel driving time, then driving time is minimized, but power consumption increases
Solution Approach 1:
The amplifier circuit uses periodic boosting action only during rising and falling periods when current flow needs to be increased. During stable high or low states, the boosting circuits remain inactive, maintaining static current mode operation. This periodic activation minimizes power consumption while achieving fast switching.
Solution Approach 2:
The circuit dynamically changes current parameters based on operating conditions. During transitions, the boosting circuits increase current flow to minimize driving time. During stable states, the circuit maintains lower static current to reduce power consumption. This parameter adaptation resolves the contradiction between speed and power consumption.
3Power
If multi-stage amplification is implemented to amplify voltage effectively, then voltage amplification is improved, but circuit complexity and manufacturing difficulty increase
Solution Approach 1:
The amplifier circuit uses uniform transistor structures (PMOS and NMOS transistors with similar configurations) across all stages. Each stage follows the same basic architecture with feedback connections, making the circuit homogeneous in structure. This homogeneity simplifies wafer-based semiconductor manufacturing while achieving effective multi-stage voltage amplification.
Data Source
AI summary
Disclosed is an amplifier circuit comprising a first stage having first and second input terminals, a second stage configured to amplify a voltage supplied from the first stage and including a pull-up node and a pull-down node, a third stage including an output terminal, a tenth PMOS transistor, and a tenth NMOS transistors having gate electrodes respectively connected to the pull-up node and the pull-down node of the second stage, the third stage configured to perform a pull-up driving and pull-down driving of the amplified voltage, a first boosting circuit including an eleventh PMOS transistor having a gate electrode connected to the pull-up node and the first boosting circuit configured to increase a current in the first stage, and a second boosting circuit including an eleventh NMOS transistor having a gate electrode connected to the pull-down node and configured to increase the current in the first stage.