Display Array Substrate Auxiliary Patterns Reduce Signal Resistance
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Solution Overview
Problem
As display devices increase in size and resolution, the length of signal lines such as gate and data lines leads to increased resistance and signal delays, while attempts to reduce resistance by widening or thickening these lines result in decreased aperture ratio and brightness, or increased manufacturing costs and material usage.
Innovation Solution
The array substrate incorporates auxiliary gate and data patterns formed by a plating method, which reduce the resistance of signal lines, improve aperture ratio, and enhance brightness by allowing for thinner lines without increasing material usage or manufacturing costs, using materials like copper, chromium, or nickel for these patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the width of signal lines is increased to reduce resistance, then resistance decreases, but pixel region area decreases and aperture ratio is reduced
Solution Approach 1:
The patent applies local quality by forming auxiliary conductive patterns selectively at specific locations along the signal lines (gate lines and data lines) rather than uniformly increasing the width of entire signal lines. These auxiliary patterns are positioned in regions where resistance accumulation is most significant, providing localized resistance reduction while preserving the overall pixel region area and aperture ratio.
2Reliability
If the thickness of signal lines is increased to reduce resistance, then resistance decreases, but manufacturing costs increase and light efficiency is lowered
Solution Approach 1:
The patent segments the signal line structure by adding separate auxiliary conductive patterns (first auxiliary gate pattern and first auxiliary data pattern) that are formed independently from the main signal lines. These auxiliary patterns are created through distinct deposition and patterning steps, allowing selective resistance reduction at critical locations without requiring uniform thickening of entire signal lines, thereby controlling material consumption and manufacturing costs.
3Illumination intensity
If display device size and resolution are increased, then display quality improves, but signal line length increases and resistance increases
Solution Approach 1:
The patent addresses the resistance issue in large-high definition display devices by transitioning from a two-dimensional signal line width adjustment to a three-dimensional structure. Auxiliary conductive patterns are formed that extend in the vertical dimension (through multiple layers including passivation layers) and are positioned at multiple locations along the horizontal signal line paths, effectively reducing resistance without increasing the planar footprint or compromising display quality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces signal line resistance, prevents signal delays, and increases aperture ratio and brightness, while simplifying the manufacturing process and reducing costs by allowing simultaneous formation of auxiliary patterns on both gate and data lines.
Implementation Method 1
auxiliary gate and data patterns formed by a plating method
Data Source
AI summary
An array substrate for a display device and manufacturing method thereof is disclosed. The device comprises: a substrate; a gate line formed on the substrate along a first direction; a data line formed over the substrate along a second direction, wherein the data line and the gate line cross each other to define a pixel region; a thin film transistor formed in the pixel region, and having a gate electrode connected to the gate line, a source electrode connected to the data line, and a drain electrode; a pixel electrode formed in the pixel region and connected to the drain electrode; a first auxiliary gate pattern formed over the gate line and contacting the gate line; and a first auxiliary data pattern formed over the data line and contacting the data line.