Display Assembly Parallel Timing Controller Bandwidth
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Solution Overview
Problem
Current display technologies face challenges in transmitting high-resolution and high-refresh-rate signals due to limited bandwidth support in the connection interface between the main control chip and the timing controller, leading to potential pixel data loss.
Innovation Solution
The implementation of a display assembly with multiple timing controllers and data driving circuits, where pixel data is divided into sets and transmitted simultaneously, along with a gate driving circuit to ensure synchronized data voltage delivery to the display panel, addressing bandwidth limitations by distributing pixel data across multiple sub-areas and using embedded display port interfaces and buffers to manage data transmission effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a single timing controller and data driving circuit are used, then the device complexity is low, but the bandwidth is insufficient to support high resolution and high refresh rate signals
Solution Approach 1:
The patent divides the pixel data transmission into multiple parallel channels by using K timing controllers (where K≥2). Each timing controller receives a portion of the pixel data (K sets of pixel data) and processes them independently. This segmentation allows the system to achieve higher total bandwidth by summing the capacity of multiple controllers, while each individual controller maintains manageable complexity.
2Speed
If pixel data is transmitted at high speed, then the refresh rate increases, but data loss occurs due to bandwidth limitations
Solution Approach 1:
By segmenting the pixel data into K sets and distributing them to K timing controllers, the patent enables parallel transmission of data subsets. This increases the overall data transmission speed while maintaining reliability because each timing controller can handle its assigned data subset within the available bandwidth, preventing data loss that would occur in a single-channel system attempting to transmit all pixel data at high speed.
Solution Approach 2:
The patent implements continuous data transmission by dividing pixel data into multiple sets that are transmitted simultaneously through different timing controllers. This parallel continuous transmission ensures that data flow remains uninterrupted and maintains high speed without causing data loss, as each controller continuously processes its assigned data subset without waiting for others to complete.
3Quantity of substance
If multiple timing controllers are used to increase bandwidth, then high resolution and refresh rate are supported, but the device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the display panel's pixel data into K subsets, where each subset is handled by a dedicated timing controller. This segmentation strategy increases the total bandwidth capacity to support high resolution and refresh rates, while each individual timing controller maintains relatively simple internal architecture, balancing the trade-off between total system bandwidth and individual component complexity.
Data Source
AI summary
A display apparatus comprises a display assembly and a main control chip. The display assembly comprises K timing controllers, K data driving circuits and a display panel. Each timing controller is configured to receive a set of pixel data among K sets of pixel data into which an i-th row of pixel data in a frame of image data are divided. A data driving circuit in the K data driving circuits is configured to receive the set of pixel data from a corresponding timing controller and output a set of data voltages. The display panel is configured to receive K sets of data voltages for display. The main control chip comprises a processor configured to receive the frame of image data, divide the i-th row of pixel data into the K sets of pixel data, and simultaneously transmit the K sets of pixel data to the K timing controllers.