Display Device Parasitic Capacitance Reduction via Asymmetric Vias
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Solution Overview
Problem
OLED display devices face issues with parasitic capacitance between metal and electrode layers, leading to signal transmission delays and degraded display quality due to the overlapping regions of these layers.
Innovation Solution
The design includes a substrate with a display region and a border region, featuring specific structures such as non-aligned openings and contact vias, where the electrode layer is not directly overlapped with the metal layer contact via, reducing parasitic capacitance by minimizing the overlapping area between the metal and electrode layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the metal layer and electrode layer are overlapped to ensure electrical connection, then the electrical connectivity is improved, but the parasitic capacitance increases
Solution Approach 1:
The patent extracts the harmful overlapping region between the metal layer and electrode layer by introducing openings in the insulating layer. This removes the parasitic capacitance source while preserving the necessary electrical connections through contact vias, directly resolving the contradiction between connectivity and capacitance reduction.
Solution Approach 2:
The patent applies different structural configurations to different regions: in the display region, the metal layer and electrode layer overlap for proper electrical connection, while in the border region, openings are introduced to prevent overlapping. This local differentiation allows the system to optimize both connectivity and capacitance reduction in their respective regions.
2Speed
If the metal layer and electrode layer are overlapped to ensure signal transmission, then the signal transmission path is established, but the signal transmission delay increases due to parasitic capacitance
Solution Approach 1:
By removing the overlapping region between metal layer and electrode layer through openings in the border region, the patent extracts the source of parasitic capacitance that causes signal transmission delay, thereby improving signal transmission speed without compromising the necessary electrical connection paths.
3Ease of manufacture
If the opening and contact via are aligned to simplify manufacturing, then the manufacturing process is simplified, but the parasitic capacitance increases due to overlapping
Solution Approach 1:
The patent introduces asymmetric positioning where the opening in the electrode layer and the contact via in the metal layer are deliberately misaligned in the border region. This asymmetric configuration prevents overlapping and reduces parasitic capacitance, while the alignment requirements are managed through the existing manufacturing process capabilities.
4Device complexity
If the first opening and second opening are aligned to simplify structure, then the structural complexity is reduced, but the parasitic capacitance between metal layer and electrode layer increases
Solution Approach 1:
The patent deliberately creates asymmetric positioning between the first opening and second opening in the border region, preventing their alignment. This asymmetric configuration ensures that the metal layer and electrode layer do not overlap, thereby reducing parasitic capacitance while accepting the increased structural complexity as a necessary trade-off for performance improvement.
Data Source
AI summary
A display device comprising: a substrate with a display region and a border region; a first metal layer disposed on the substrate; a first insulating layer disposed on the first metal layer and having a first contact via on the border region; a second metal layer disposed on the first insulating layer and in the first contact via to electrically connect to the first metal layer; a second insulating layer disposed on the second metal layer; a first electrode layer disposed on the second insulating layer and having a first opening; a third insulating layer disposed on the first electrode layer and has a second opening on the border region; and a second electrode layer disposed on the third insulating layer and in the second opening to electrically connect to the first electrode layer, wherein the first contact via corresponds to the first opening, is disclosed.