Display Baseplate Layout for High-PPI Oxide TFT Stability
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Solution Overview
Problem
The increasing demand for higher pixels per inch (PPI) in display panels leads to a reduction in capacitor area for pixel circuits, making them more susceptible to electric leakage. Additionally, oxide thin film transistors are affected by hydrogen, oxygen, and doping agents from low temperature polycrystalline silicon thin film transistors, causing characteristic drift and requiring larger pixel circuit spaces.
Innovation Solution
A display baseplate design that includes a substrate with a polycrystalline silicon thin film transistor structure layer, an insulation layer, and an oxide thin film transistor structure layer. The insulation layer is positioned between the two transistor structure layers to block the diffusion of hydrogen, oxygen, and doping agents, and there is a time interval between the preparation processes of the two transistor layers to further prevent interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If oxide thin film transistor is placed close to polycrystalline silicon thin film transistor to reduce space, then pixel circuit occupies smaller space, but oxide thin film transistor is affected by hydrogen, oxygen and doping agent diffusion causing characteristic drift
Solution Approach 1:
An insulation layer is introduced as an intermediary barrier between the polycrystalline silicon thin film transistor structure and the oxide thin film transistor structure. This insulation layer prevents the diffusion of hydrogen, oxygen, and doping agents from the polycrystalline silicon side to the oxide thin film transistor side, thereby protecting the oxide transistor characteristics while allowing the structures to be positioned close together for space efficiency.
2Reliability
If insulation layer thickness is increased to better block diffusion, then protection of oxide thin film transistor is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The insulation layer is constructed as a composite structure comprising multiple film layers with different materials and functions. This includes a first insulation film layer (e.g., silicon nitride) that blocks ion diffusion, a second insulation film layer (e.g., silicon oxide) that provides electrical insulation and serves as an etch stop layer, and optionally a third film layer for additional protection. This composite approach achieves effective diffusion blocking while managing the complexity through functional integration of multiple layers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design allows for a partial overlap of the polycrystalline silicon and oxide semiconductor active layers, reducing the pixel circuit's space occupancy and enhancing PPI, while also preventing parasitic capacitor formation and maintaining the reliability of the pixel circuit.
Implementation Method 1
the insulation layer can block diffusion of hydrogen element, oxygen element and a doping agent generated by a polycrystalline silicon active layer toward an oxide semiconductor active layer
Data Source
AI summary
Display baseplates, display panels and display apparatuses are provided. A display baseplate includes a substrate, a polycrystalline silicon thin film transistor structure layer located on the substrate, an insulation layer located at a side of the polycrystalline silicon thin film transistor structure layer away from the substrate, an oxide thin film transistor structure layer located at a side of the insulation layer away from the substrate, and a plurality of sub-pixels located on the substrate, at least one of the sub-pixels includes a light-emitting element and a pixel circuit for driving the light-emitting element and including a polycrystalline silicon active layer located on the polycrystalline silicon thin film transistor structure layer and an oxide semiconductor active layer located on the oxide thin film transistor structure layer; orthographic projections of both the polycrystalline silicon active layer and the oxide semiconductor active layer on the substrate are at least partially overlapped.