Display Baseplate Gate Driving Layout for OLED Row Luminance Uniformity

The gate driving circuit is segmented into two independent architectures: a 1-driving-1 architecture for odd rows and a 1-driving-2 architecture for even rows. This segmentation allows each row type to have optimized charging paths, eliminating the fine horizontal-stripe defects caused by uniform architecture while managing overall system complexity through modular design.

Different capacitance values are assigned to pixel driving circuits based on their row position: odd rows use one capacitance value while even rows use another. This local quality differentiation compensates for the inherent charging time differences between row types, achieving luminance uniformity across the display while maintaining manufacturability through standardized component libraries.

The channel width-to-length ratio of transistors is adjusted as a key parameter to balance charging times between odd and even rows. By optimizing this geometric parameter, the patent achieves synchronized charging completion across different row architectures without requiring fundamental circuit redesign, thus managing device complexity while improving timing uniformity.

Control signals are designed with periodic, non-overlapping duration patterns for odd and even rows. This periodic timing scheme ensures that charging operations in different rows are synchronized without interference, reducing luminance differences while maintaining manageable signal complexity through repetitive, predictable timing sequences.