Display Bezel Compensation for Luminance Uniformity
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Solution Overview
Problem
Display panels with free form portions, such as curved or notched shapes, experience luminance nonuniformity due to differences in the number of pixels and resistor-capacitor (R-C) load variations between free form and non-free form areas, leading to signal delay and degraded display quality.
Innovation Solution
Incorporating a compensating unit in the bezel area with semiconductor patterns, dummy gate lines, and power supply electrodes to form compensation capacitances, which are connected through contact holes and dummy holes to adjust the R-C load and improve luminance uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a display panel with a free form portion (curved or notched shape) is used to increase design freedom, then product design appeal is improved, but luminance nonuniformity occurs due to R-C load variation between different regions
Solution Approach 1:
The patent applies local quality by introducing compensating units with different structures in different regions of the display panel. Specifically, regions with free form portions (curved or notched) have compensating units with adjusted semiconductor patterns, gate lines, and power supply electrodes to compensate for the reduced pixel count and R-C load variation, while regions without free form portions use standard compensating units. This localized adaptation maintains luminance uniformity across the entire display while preserving the design freedom of free form portions.
2Adaptability or versatility
If the number of pixels per line varies in free form portions compared to non-free form portions, then design flexibility is improved, but signal delay between lines is generated due to R-C load difference
Solution Approach 1:
The patent applies parameter changes by modifying the R-C load parameters in compensating units located in free form portions. The compensating units adjust the number and arrangement of semiconductor patterns, gate lines, and power supply electrodes to change the effective capacitance and resistance values. This parameter adjustment compensates for the R-C load difference caused by varying pixel counts per line, thereby eliminating signal delay between lines while maintaining design flexibility.
3Reliability
If compensating units are added to the bezel area to compensate for R-C load differences, then luminance uniformity is improved, but device complexity increases
Solution Approach 1:
The patent applies merging by integrating the compensating units into the existing bezel area structure. The compensating units share common elements with the display panel infrastructure, such as using the same substrate, insulating layers, and connection methods. The compensating units are formed using the same manufacturing processes as the main display panel, merging the compensation function into the existing device architecture rather than adding separate complex structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively compensates for R-C load differences, enhancing luminance uniformity and display quality by adjusting the capacitance and charge time across the display panel, particularly in areas with curved or notched shapes.
Implementation Method 1
a plurality of dummy gate lines which is disposed between the semiconductor patterns and the power supply electrode, overlaps the semiconductor pattern to form a first compensation capacitance and overlaps the power supply electrode to form a second compensation capacitance
Data Source
AI summary
Provided is a display apparatus. The display apparatus includes an active area and a bezel area, the display apparatus comprising semiconductor patterns disposed in a third area of the bezel area, an insulating layer disposed on the semiconductor patterns and includes contact holes and dummy holes, a power supply electrode disposed in the third area of the bezel area, overlaps the semiconductor patterns with the insulating layer therebetween, and is connected to the semiconductor patterns through the contact holes, dummy gate lines disposed between the semiconductor patterns and the power supply electrode, overlap the semiconductor pattern to form a first compensation capacitance and overlap the power supply electrode to form a second compensation capacitance, and a dummy semiconductor patterns disposed in the third area of the bezel area, and are connected to the power supply electrode through the dummy holes.