Display Device Bezel Minimization via Overlapping Circuit Lines
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Solution Overview
Problem
Existing liquid crystal display (LCD) devices have a limited ability to minimize the bezel area due to the complexity of their structure and manufacturing processes, which increases costs and the likelihood of defects.
Innovation Solution
The solution involves overlapping circuit lines in the dummy region with an insulating layer interposed between them, directly connecting thin film transistors (TFTs) to control signal lines, and forming contact holes along these lines to reduce the width of the dummy region and minimize the bezel area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If circuit lines are arranged in a conventional non-overlapping manner in the dummy region, then the manufacturing process is simpler, but the bezel area cannot be minimized
Solution Approach 1:
The patent applies dimensionality change by transitioning from a planar arrangement of circuit lines to a three-dimensional overlapping arrangement. Control signal lines are formed to overlap with the GIP circuit and dummy gate driver in the vertical dimension, utilizing the z-axis space between substrates. This allows the circuit lines to occupy the same planar footprint while maintaining electrical isolation through insulating layers, thereby minimizing the bezel area without causing signal interference.
Solution Approach 2:
The patent introduces insulating layers as intermediary elements between overlapping circuit lines. These insulating layers act as mediators that prevent electrical short circuits while allowing the circuit lines to be positioned in close proximity or overlap in the planar view. The insulating layers enable the overlapping arrangement by providing electrical isolation, thus resolving the contradiction between minimizing bezel area and maintaining manufacturing simplicity.
2Area of stationary object
If the dummy region width is reduced to minimize bezel area, then the bezel becomes narrower, but the manufacturing process becomes more complex and costly
Solution Approach 1:
The patent merges the arrangement of control signal lines with the GIP circuit and dummy gate driver by forming them in an overlapping configuration. This merging allows the control signal lines to be integrated within the same planar region as the GIP circuit, eliminating the need for separate dedicated spaces. The overlapping arrangement combines multiple functional elements into a compact structure, reducing the dummy region area while maintaining manufacturability through systematic layer formation.
Solution Approach 2:
The patent utilizes the vertical dimension between substrates to arrange control signal lines in overlap with the GIP circuit. By forming control signal lines on different layers that overlap in the planar view but are separated vertically by insulating layers, the design achieves compact integration without compromising manufacturing processes. This dimensional approach allows standard manufacturing techniques to be applied while achieving reduced dummy region area.
3Area of stationary object
If control signal lines are directly connected to TFTs through contact holes, then the bezel area is minimized, but the risk of manufacturing defects increases
Solution Approach 1:
The patent introduces insulating layers as intermediary elements between overlapping circuit lines and TFT structures. These insulating layers serve as protective mediators that prevent direct contact and potential short circuits between conductive elements. By positioning insulating layers between the control signal lines and TFTs, the design enables direct connections through contact holes while maintaining reliable electrical isolation, thus reducing defect risk in the compact overlapping arrangement.
Data Source
AI summary
A display device including a first substrate. The first substrate including an active region and a dummy region formed in an outer edge of the active region, the active region including a plurality of pixel regions and being configured to implement an actual image, the dummy region including a gate in panel (GIP) circuit, control signal lines, a ground, and common lines. The GIP circuit is overlapped by at least a part of the control signal lines, the ground, and the common lines with an insulating layer interposed therebetween. The display device further includes a thin film transistor (TFT) for a shift register is provided in each of a plurality of stages of the GIP circuit; and a source contact hole and a gate contact hole of each TFT for the shift registers, the source contact hole and the gate contact hole being formed along a corresponding control signal line.