Display Blank Period Synchronization for CPU Power Saving
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Solution Overview
Problem
During CPU power saving processes, the integration of system memory controller within the CPU leads to data transmission breaks between system memory and graphics-processing units, disrupting continuous graphics or video data display on multiple display devices.
Innovation Solution
The implementation of four image data display mechanisms that synchronize or adjust the blank periods of display devices to execute power saving processes within overlapping or least common multiple blank periods, ensuring continuous display without constraints on resolution or number of devices, as long as system bandwidth is sufficient.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If the CPU executes power saving processes by adjusting operating frequency, then power consumption is reduced, but graphics display continuity is disrupted due to memory access interruptions
Solution Approach 1:
The patent segments the display refresh cycle into active display periods and blank periods, allowing CPU power saving operations to be performed during the blank period when no display data is being transmitted. This segmentation enables the CPU to adjust its operating frequency during the blank period without affecting display continuity, as the display hardware continues to receive data during active periods while the CPU operates at reduced frequency during blank periods.
Solution Approach 2:
The patent implements preliminary action by pre-synchronizing multiple display devices to share common blank periods before CPU power saving operations are initiated. The system detects and aligns the blank periods of multiple display devices in advance, ensuring that when the CPU enters power saving mode, all display devices are already synchronized to their blank periods, thus preventing any display interruption while enabling power savings.
2Productivity
If the CPU operates at high frequency to maintain processing performance, then graphics display responsiveness is improved, but power consumption increases
Solution Approach 1:
The patent applies periodic action by cycling the CPU between high-frequency operation during active display periods and low-frequency operation during blank periods. The CPU dynamically adjusts its operating frequency in sync with the display refresh cycle, operating at full speed when display data must be processed and transmitted, then switching to a lower frequency during blank periods when no display output is required. This periodic frequency adjustment maintains display responsiveness while reducing average power consumption.
3Adaptability or versatility
If multiple display devices are connected with different refresh rates, then display versatility is increased, but synchronizing blank periods for CPU power saving becomes complex
Solution Approach 1:
The patent implements universality by creating a synchronization mechanism that works with display devices of any refresh rate. The system detects the refresh rates of multiple display devices and calculates a common synchronization period that accommodates all devices. This universal approach allows the CPU to execute power saving operations during synchronized blank periods regardless of the specific refresh rates of connected display devices, maintaining versatility while managing complexity through a standardized synchronization protocol.
Data Source
AI summary
The present invention provides an image/graphics data display mechanism for continuously displaying image/graphics data on multiple display devices of a computer that contains a system memory directly accessed by the computer's CPU during the CPU's power saving non-responding period, wherein there is provided sufficient system bandwidth, the mechanism of the present invention is independent on the resolution running on each display device and the number of display devices connected to the computer system. The mechanism provides two approaches to achieve continuous display of image/graphics data on multiple display devices computer system. In the first approach, a common clock source is used to coordinate display device horizontal synchronization signals, vertical synchronization signals, horizontal blank periods, and vertical blank periods. In the second approach, the mechanism has a control on the lengths and occurrences of the display device blank periods.