Display Panel Bonding Region Layout for Dense IC Pin Routing
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Solution Overview
Problem
The high cost of fabricating integrated circuits and the need for a more efficient bonding method in display panels to reduce the number of integrated circuits required.
Innovation Solution
A display panel design featuring a bonding region with a base substrate and multiple bonding pin structures arranged in columns, where each bonding pin structure includes a bonding pin and connection lines on both ends, and the connection lines are alternately layered in a first and second conductive layer to prevent shorts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple bonding pins and connection lines are arranged in a single layer, then the layout is simple, but the density of bonding pins per unit area is low
Solution Approach 1:
The patent transitions from a single-layer arrangement to a multi-layer arrangement of connection lines. Specifically, connection lines are distributed across first, second, and third conductive layers, allowing bonding pins to be densely packed in the bonding region without short-circuiting. This dimensional transition from 2D plane to 3D space enables higher bonding pin density while maintaining electrical isolation between adjacent lines through the insulating layers separating the conductive layers.
2Reliability
If connection lines are placed in the same layer, then the manufacturing process is simpler, but the risk of short circuits between adjacent lines increases
Solution Approach 1:
The patent segments the connection lines into multiple independent conductive layers (first, second, and third conductive layers), with insulating layers between them. This segmentation physically separates adjacent connection lines that would otherwise be in the same layer, eliminating the short circuit risk while maintaining manufacturing feasibility through standard multi-layer PCB fabrication processes.
Solution Approach 2:
Insulating layers are introduced as intermediary elements between adjacent conductive layers. These insulating layers provide electrical isolation and prevent short circuits between connection lines in different layers, while allowing the lines to pass through the same bonding region. The insulating layers act as mediators that enable high-density routing without compromising electrical reliability.
3Quantity of substance
If bonding pins are arranged in fewer rows, then the manufacturing process is simpler, but the total number of bonding pins that can be integrated is limited
Solution Approach 1:
By introducing multiple conductive layers (first, second, and third conductive layers) stacked vertically, the patent effectively adds a Z-dimension to the bonding region layout. This allows bonding pins to be arranged in multiple rows (first, second, third, and fourth rows) with connection lines routed through different layers, significantly increasing the total bonding pin count that can be integrated in a given footprint area.
Data Source
AI summary
A display panel having a bonding region for bonding an integrated circuit is provided. The display panel includes a base substrate; and a plurality of bonding pin structures on the base substrate arranged in a plurality of columns, respectively. A respective bonding pin structure includes a respective bonding pin and connection lines on two ends of the respective bonding pin, respectively. Bonding pins of the plurality of bonding pin structures are arranged in N rows, N is a positive integer equal to or greater than 4. (N−1) number of connection lines pass through a region between two adjacent bonding pins arranged in a same row.