Non-Interrupt Display Buffering via Swap Register
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Solution Overview
Problem
In safety-critical environments, traditional methods for buffering images between a GPU and display controller, such as triple buffering, rely on interrupts which can be undesirable or impossible, leading to difficulties in ensuring reliability and avoiding errors or race conditions, especially when coordinating between different cores with shared memory is not feasible.
Innovation Solution
A method and system for non-interrupt-based asynchronous display buffering using multiple frame buffers, where a processor writes data to a selected frame buffer, sends a swap buffer signal to the GPU, and the display controller updates to set the ready frame buffer as the front buffer during display synchronization intervals, allowing the GPU and display controller to operate independently without interrupts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional triple buffering with interrupts is used, then coordination between GPU and display controller is achieved, but system reliability decreases and complexity increases in safety-critical environments
Solution Approach 1:
The patent removes the interrupt mechanism from the buffering system, extracting the coordination function from the CPU interrupt handler and implementing it through direct GPU-to-display-controller communication. This eliminates the complexity and reliability issues associated with interrupts in safety-critical environments while maintaining the essential coordination between rendering and display components.
Solution Approach 2:
The patent introduces a buffer swap register as an intermediary mechanism between the GPU and display controller. This register serves as a simple, reliable signal that the GPU writes to indicate buffer readiness, eliminating the need for complex interrupt handling while maintaining coordination. The register acts as a mediator that enables direct communication without CPU involvement.
2Productivity
If interrupts are used for buffer coordination, then frame data flow is maintained, but latency increases and performance decreases
Solution Approach 1:
The patent implements preliminary action by having the GPU proactively write to the buffer swap register as soon as a frame is ready, before the display controller needs to read it. This anticipatory approach eliminates waiting time and ensures that the display controller can immediately switch to the ready buffer during the next vertical sync, reducing latency and improving frame data flow efficiency.
3Reliability
If CPU coordinates data exchange between GPU and display controller, then data synchronization is achieved, but CPU overhead increases and system performance decreases
Solution Approach 1:
The patent implements self-service by enabling the GPU and display controller to coordinate buffer swaps autonomously without CPU intervention. The GPU writes to the buffer swap register to signal readiness, and the display controller reads this register during vertical sync to determine which buffer to display. This self-service mechanism eliminates CPU overhead and energy consumption associated with interrupt handling and coordination.
Data Source
AI summary
Methods and systems for multiple-buffered display rendering without the use of hardware or software interrupts. In a first repeating process, a processor writes data for a frame a selected frame buffer and, upon completion of the frame, a swap buffer signal is transmitted. In response to the swap buffer signal, the GPU updates a memory register of the display controller to indicate that the selected frame buffer can be used in the next display synchronization interval. In a separate repeating process, the display controller monitors memory register and, in a display synchronization interval, identifies the frame buffer to use for display.