Display Device Bypass Write for Image Data Transfer
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional display devices require two steps of reading and writing to transfer image data, resulting in prolonged process time without significant improvements in processing capacity.
Innovation Solution
A display device with a first memory, a second memory, and two controllers where the first controller outputs a read signal to the first memory, and the second controller directly reads and writes the image data from the data bus, bypassing the first controller, allowing for a single-step transfer of image data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the CPU reads image data from ROM before writing to VRAM via GDC, then the image data can be transferred, but the process time is prolonged due to requiring two separate steps of reading and writing
Solution Approach 1:
The patent merges the reading and writing operations into a single simultaneous step. The GDC directly reads image data from ROM and writes it to VRAM concurrently, eliminating the sequential two-step process (CPU read then CPU write) and significantly reducing transfer time without requiring additional processing capacity.
2Productivity
If the CPU performs sequential reading and writing operations, then data integrity is maintained, but the processing capacity remains insufficient due to the two-step process
Solution Approach 1:
The GDC serves as an intermediary that enables direct data transfer between ROM and VRAM. By allowing the GDC to perform both reading from ROM and writing to VRAM simultaneously, the system achieves higher processing capacity without adding more controllers or complex processing logic, thus improving productivity without proportionally increasing device complexity.
Data Source
AI summary
For providing a display device and a method for transferring an image data, shortening process time required to transfer image data without greater processing capacity, the CPU 4 outputs the bypass write signal to the GDC 6, the CPU 4 then outputs the read signal to both the ROM 5 and the GDC 6, and the ROM 5 outputs the image data to the data bus 8 according to input of the read signal, wherein the GDC 6 directly reads the image data outputted on the data bus 8 according to input of the read not through the CPU 4 and writes the read image data to the VRAM 7.