Display Controller Caching During Memory Clock Retraining
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Solution Overview
Problem
Managing memory bandwidth in multiple-display systems is challenging due to the difficulty in finding a convenient time to halt all memory accesses during memory clock frequency changes without introducing visual artifacts.
Innovation Solution
Implementing a caching mechanism to prefetch frame data into a cache before performance-state changes, allowing requests to be serviced from the cache during memory blackout periods, thereby maintaining display quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If memory clock frequency is changed to reduce power consumption during reduced memory accesses, then power consumption is reduced, but visual artifacts are introduced due to required memory interface retraining that temporarily stops memory accesses
Solution Approach 1:
The system performs a preliminary action by caching display data in advance before the memory interface retraining occurs. The display controller caches at least one frame of display data in cache memory before the memory clock frequency change and associated retraining, ensuring that display data is available during the blackout period when memory accesses are stopped, thus preventing visual artifacts while allowing power reduction
2Productivity
If memory clock frequency is increased to process large numbers of reads and writes during multiple workloads, then processing capability is improved, but power consumption increases
Solution Approach 1:
The system dynamically adjusts the memory clock frequency based on workload conditions. The memory interface operates at a first (higher) clock frequency when multiple workloads require large numbers of reads and writes, and switches to a second (lower) clock frequency when memory accesses are reduced, optimizing the balance between processing capability and power consumption in real-time
3Loss of energy
If memory interface retraining is performed to change memory clock frequency, then power consumption is optimized, but memory accesses must be temporarily stopped causing display interruptions
Solution Approach 1:
The system introduces an intermediary solution by using cache memory as a buffer between the frame buffer and display controller during memory interface retraining. The cache memory serves as a temporary storage that decouples the display data supply from memory accesses, allowing the memory interface to be retrained without causing display interruptions or visual artifacts
Data Source
AI summary
Systems, apparatuses, and methods for prefetching data by a display controller. From time to time, a performance-state change of a memory are performed. During such changes, a memory clock frequency is changed for a memory subsystem storing frame buffer(s) used to drive pixels to a display device. During the performance-state change, memory accesses may be temporarily blocked. In order to reduce visual artifacts that may occur while the memory accesses are blocked, a memory subsystem includes a control circuit configured to enable a caching mode which caches display data provided to the display controller. Subsequent requests for display data from the display controller are then serviced using the cached data instead of accessing memory.