Display Substrate Capacitor Layout for Compact 8K GOA Circuits
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Solution Overview
Problem
The development of 8K display devices is hindered by the difficulty in creating a suitable Gate Driver on Array (GOA) due to increased Pixel Per Inch (PPI), which restricts layout space and leads to issues like short circuits during capacitor electrode plate connections, causing circuitry failures.
Innovation Solution
A display substrate design featuring a three-layer capacitor structure with specific orthogonal projections and via-holes to prevent electrical connections between conductive patterns, reducing the probability of short circuits and optimizing layout space, while using a metal material for conductive patterns and a shared gate electrode to reduce manufacturing costs and thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the resolution is increased to 8K or more, then the display quality is improved, but the layout space is restrained due to increased PPI
Solution Approach 1:
The patent transitions from a conventional planar capacitor structure to a three-dimensional stacked structure with multiple conductive patterns arranged in different layers (first, second, and third conductive patterns at different heights). This vertical arrangement in the Z-dimension reduces the horizontal footprint of the capacitor, thereby saving layout space while maintaining capacitance functionality for high-resolution 8K displays
Solution Approach 2:
The patent implements a nested structure where the second conductive pattern is positioned within the projection area of the first conductive pattern, and the third conductive pattern is positioned within the projection area of the second conductive pattern. This nested arrangement maximizes space utilization and reduces the overall area occupied by the capacitor structure
2Measurement precision
If the layout space is reduced to accommodate higher PPI, then the display resolution is improved, but the probability of short circuits increases
Solution Approach 1:
The capacitor structure is segmented into multiple independent conductive patterns (first, second, and third conductive patterns) separated by insulation layers. This segmentation creates physical barriers that prevent unintended electrical connections, reducing short circuit probability while enabling compact layout for high-resolution displays
Solution Approach 2:
Insulation layers are introduced as intermediary elements between the conductive patterns. These insulation layers act as protective mediators that prevent direct contact between adjacent conductive patterns, thereby eliminating short circuit risks while allowing the conductive patterns to be positioned close together for space efficiency
3Ease of manufacture
If the capacitor structure is simplified to reduce manufacturing complexity, then the ease of manufacture is improved, but the short circuit protection is reduced
Solution Approach 1:
The patent combines multiple functions into the capacitor structure: the conductive patterns serve both as capacitor electrodes and as light-shielding layers. This merging reduces the total number of manufacturing steps and material layers while maintaining short circuit protection through the integrated insulation design
Data Source
AI summary
A display substrate includes: a base substrate; a first conductive pattern arranged on the base substrate; a first insulation layer arranged at a side of the first conductive pattern away from the base substrate; a second conductive pattern arranged at a side of the first insulation layer away from the base substrate; a second insulation layer arranged at a side of the second conductive pattern away from the base substrate; and a third conductive pattern arranged at a side of the second insulation layer away from the base substrate. The third conductive pattern and the first conductive pattern together serve as a first electrode plate of the capacitor, and the second conductive pattern serves as a second electrode plate of the capacitor.


