Display Capacitor Layout for Alignment-Tolerant Capacitance
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Solution Overview
Problem
Display devices face issues in maintaining uniform capacitance of capacitors due to alignment errors between the active layer and the second metal layer during manufacturing.
Innovation Solution
The display device incorporates a cover pattern in the second metal layer, spaced apart from a connection electrode, with equal widths in a specific direction, to maintain capacitor capacitance uniformity even when alignment errors occur.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If alignment between active layer and second metal layer is performed during manufacturing, then capacitor capacitance uniformity is improved, but manufacturing precision requirements increase and production complexity worsens
Solution Approach 1:
The patent applies preliminary action by pre-defining the geometric relationship between the cover pattern and connection electrode before alignment occurs. The cover pattern is designed with specific width equal to the connection electrode width, and positioned to overlap the capacitor electrode in plan view, creating a built-in compensation mechanism that works automatically regardless of alignment variations.
Solution Approach 2:
The patent changes the geometric parameters of the cover pattern and connection electrode, specifically setting their widths equal in the second direction and positioning them to overlap the capacitor electrode. This parameter configuration creates a tolerance window that maintains capacitance uniformity despite alignment errors, transforming the system from being sensitive to alignment parameters to being robust against them.
2Device complexity
If alignment errors occur during manufacturing, then production complexity is reduced, but capacitor capacitance uniformity deteriorates
Solution Approach 1:
The patent implements beforehand cushioning by designing the cover pattern to overlap the capacitor electrode in plan view, creating a protective geometric configuration before alignment errors occur. This overlap creates a buffer zone that absorbs alignment variations, cushioning the impact of manufacturing imprecision on capacitor capacitance uniformity.
Solution Approach 2:
The patent modifies the geometric parameters of the cover pattern and connection electrode, setting their widths equal in the second direction and positioning them to overlap the capacitor electrode. This parameter configuration creates a tolerance window that maintains capacitance uniformity despite alignment errors, transforming the system from being sensitive to alignment parameters to being robust against them.
3Manufacturing precision
If cover pattern width is increased to compensate for alignment errors, then capacitor capacitance uniformity is improved, but device area increases
Solution Approach 1:
The patent optimizes the width parameter of the cover pattern and connection electrode, setting them equal in the second direction. This specific parameter configuration provides the minimum necessary overlap to maintain capacitance uniformity while minimizing the area occupied, achieving a balance between capacitance control and area efficiency.
Data Source
AI summary
A display device includes a first voltage line disposed in a first metal layer on a substrate and extending in a first direction, a first transistor including a source electrode disposed in an active layer on the first metal layer and a gate electrode disposed in a second metal layer on the active layer, the first transistor being electrically connected to the first voltage line, a first connection electrode disposed in the second metal layer and integrally formed with the gate electrode of the first transistor, a cover pattern disposed in the second metal layer and spaced apart from the first connection electrode in the first direction, and a first capacitor including a first capacitor electrode disposed in the active layer and electrically connected to the gate electrode of the first transistor, and a second capacitor electrode disposed in the first metal layer and electrically connected to the source electrode of the first transistor. A first side of the cover pattern and a first side of the first connection electrode facing each other overlap the first capacitor electrode in a plan view.