Display Panel Capacitor Structure for Higher Opening Ratio
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Solution Overview
Problem
The existing display panel technologies face limitations in achieving an improved opening ratio, particularly in organic light emitting display devices, which affects the efficiency and performance of the light emitting devices due to structural constraints and etching processes.
Innovation Solution
A manufacturing method for a display panel that includes forming a pixel circuit with a thin film transistor structure and a light emitting device, utilizing a specific etching process involving halftone mask patterning and wet etching to create a storage capacitor with a double-layer middle electrode composed of indium gallium zinc oxide (IGZO) and molybdenum titanium (MoTi), enhancing the opening ratio and reducing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a conventional etching process is used to form the active layer, then the manufacturing process is simpler, but TAIL patterns form and reduce the opening ratio
Solution Approach 1:
The active layer is divided into a first active layer (IGZO) and a second active layer (MoTi) with different etching characteristics. The first active layer is etched using wet etching while the second active layer is etched using dry etching, allowing selective removal of material and prevention of TAIL pattern formation. This segmentation enables precise control over the etching process to maintain high opening ratios.
Solution Approach 2:
Different regions of the active layer are given different material compositions tailored to their specific functions. The first active layer (IGZO) provides good etching selectivity for wet etching processes, while the second active layer (MoTi) provides good etching selectivity for dry etching processes. This local differentiation of material properties allows each layer to be optimized for its specific etching requirements, preventing TAIL pattern formation while maintaining manufacturing feasibility.
2Reliability
If the buffer layer thickness is increased to improve device reliability, then the HUMP phenomenon increases, but device reliability improves
Solution Approach 1:
The buffer layer thickness is precisely controlled within a specific range (50-150 nm) to optimize the balance between device reliability and HUMP phenomenon suppression. Additionally, the buffer layer composition is optimized (silicon oxide or silicon nitride with specific stoichiometry) to achieve the desired electrical and mechanical properties. By carefully adjusting these parameters, the buffer layer provides adequate insulation and mechanical support while minimizing the HUMP effect that would otherwise degrade device performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method increases the opening ratio and improves the reliability of the display panel by preventing the formation of TAIL patterns, reducing the HUMP phenomenon, and enhancing the success rate of cell repair, thereby improving device characteristics and efficiency.
Implementation Method 1
applying a photoresist material on the second active layer, forming a photoresist pattern through a halftone mask
Implementation Method 2
The first patterning step includes dry etching. The second patterning step includes wet etching.
Implementation Method 3
The first patterning step includes dry etching. The second patterning step includes wet etching.
Implementation Method 4
the etching is excessively performed so that a portion of the buffer layer disposed under the first active layer is etched together
Data Source
AI summary
A display panel having an improved opening ratio and a manufacturing method of the display panel are discussed. In the display panel, a storage capacitor includes a bottom electrode, a buffer layer disposed on the bottom electrode, a middle electrode covering a portion of the buffer layer, a gate insulating layer covering the middle electrode and the buffer layer, and an upper electrode covering a portion of the gate insulating layer. In the buffer layer, a thickness of a first area covering the middle electrode is greater than a thickness of a second area that is in contact with the gate insulating layer.