Display Substrate Capacitor Stack for High-PPI Voltage Stability

The patent transitions from a single-layer storage capacitor structure to a multi-layer stacked structure (first, second, and third conductive layers), effectively adding vertical dimension to increase capacitance. The first conductive layer forms a first storage capacitor, the second conductive layer forms a second storage capacitor, and the third conductive layer forms a third storage capacitor, with all three capacitors connected in parallel to achieve cumulative capacitance increase while maintaining reduced pixel dimensions.

The patent combines multiple storage capacitors (first, second, and third storage capacitors) in parallel within each pixel region, merging their capacitance values to achieve the required total capacitance. The conductive patterns of different layers are electrically connected through conductive holes, effectively combining the capacitive elements to solve the capacitance deficiency caused by pixel size reduction.

The conductive layers serve multiple functions: the first, second, and third conductive layers simultaneously form three separate storage capacitors and provide electrical connections through conductive holes. This multi-functionality reduces the need for additional dedicated structures, thereby limiting the increase in device complexity while achieving the capacitance enhancement goal.

The patent implements a nested structure where conductive holes are formed within the multi-layer conductive structure to provide electrical connections between layers. The conductive patterns in different layers are nested within each other's projection areas, creating a compact integrated structure that increases capacitance without proportionally increasing overall device complexity.