Display Channel Light-Blocking Layout for Stable Opening Rate
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Solution Overview
Problem
Electronic devices with high resolution are prone to reduced opening rates due to factors such as process variations and ambient light affecting the channel area, leading to issues like liquid crystal disclination and color mixing.
Innovation Solution
The electronic device incorporates a light blocking layer with specific width and positional relationships to the channel area, data lines, and spacers to enhance the opening rate by blocking ambient light and stabilizing liquid crystal arrangements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If high resolution is implemented in electronic devices, then display quality is improved, but opening rate drops due to process variations and ambient light affecting the channel area
Solution Approach 1:
The patent applies local quality by introducing a light blocking layer with specific width (WLS1) positioned at a critical location where it overlaps with the channel area of the semiconductor layer. This localized light blocking structure selectively addresses the ambient light interference problem in the channel region without affecting other areas of the display device, thereby maintaining high resolution while preventing opening rate degradation
Solution Approach 2:
The patent implements preliminary anti-action by placing the light blocking layer in advance to counteract the harmful effects of ambient light on the channel area before the liquid crystal molecules can be affected. The light blocking layer with width WLS1 satisfying WG≤WLS1≤10×WG pre-establishes protection against light interference, preventing liquid crystal disclination and color mixing that would otherwise occur due to ambient light exposure
2Reliability
If the metal layer width is increased to block ambient light, then liquid crystal disclination is reduced, but the device complexity increases
Solution Approach 1:
The patent applies parameter changes by precisely controlling the width parameter of the light blocking layer (WLS1) to satisfy the relational expression WG≤WLS1≤10×WG. This parameter optimization ensures sufficient light blocking capability to prevent liquid crystal disclination while avoiding excessive width that would increase device complexity. The gate line width (WG) serves as a reference parameter to standardize the light blocking layer dimensions
Solution Approach 2:
The patent implements universality by designing the light blocking layer to serve multiple functions simultaneously: it blocks ambient light from affecting the channel area, prevents liquid crystal disclination, reduces color mixing, and maintains compatibility with existing gate line structures. The light blocking layer integrates seamlessly with the existing display device architecture, avoiding the need for separate complex anti-disclination structures
Data Source
AI summary
An electronic device including a substrate, a gate line, two adjacent data lines, a semiconductor layer and a metal layer is provided. The gate line is disposed on the substrate and extends along a first direction. The two adjacent data lines are disposed on the substrate and intersects with the gate line. The semiconductor layer is disposed on the substrate and has a channel area. The metal layer is disposed between the substrate and the semiconductor layer, wherein the metal layer are overlapped with the two adjacent data lines. The metal layer has a section overlapped with the channel area, the section has a first width (WLS1) along a second direction perpendicular to the first direction, the gate line has a second width (WG) along the second direction, and the first width and the second width satisfy a relational expression below:WG≤WLS1≤10*WG.