Display Driver Chip Equalization Using BER Feedback and CDR
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Solution Overview
Problem
The increasing number of connection wires between display driver chips and timing controllers complicates design and increases manufacturing costs, while auto-equalization processes in source driver chips consume time and cause power fluctuations, leading to poor image quality.
Innovation Solution
A display driver chip with integrated automatic equalization circuits that utilize vertical blank intervals to optimize equalization, including a data receiving part, clock data recovery, bit error rate test, and equalization option control, to provide high-quality image data without errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the number of connection wires between driver chips and timing controller is increased to support larger display screens, then the display can handle larger screen sizes, but the design complexity and manufacturing cost increase
Solution Approach 1:
The patent combines multiple connection wires into a single differential signal line pair (DS0/DS1) that carries both data and clock signals. This merging approach reduces the number of physical wires from multiple separate lines to just two wires, directly resolving the contradiction between supporting larger display areas and reducing connection wire complexity
Solution Approach 2:
The differential signal line pair serves multiple functions simultaneously: it transmits data signals, recovers clock signals through CDR, and provides equalization through the EQ pin. This multi-functionality allows a single wire pair to replace what would traditionally require multiple separate wires, reducing overall connection complexity while maintaining support for large display screens
2Reliability
If auto-equalization is performed in source driver chips to optimize data reception, then data reception quality improves, but processing time and power consumption increase
Solution Approach 1:
The patent performs equalization calibration before the actual data transmission begins. The equalizer is pre-configured with optimal parameters during an initialization phase, so that when data reception starts, the equalization is already optimized and does not require continuous processing time during normal operation. This preliminary action separates the calibration phase from the data reception phase, minimizing time loss
Solution Approach 2:
The equalization process is implemented as a periodic calibration that occurs at specific intervals (such as during vertical blanking intervals) rather than continuously. This allows the equalizer to update its parameters periodically without interfering with continuous data reception, thereby maintaining data reception quality while minimizing processing time during active transmission
3Reliability
If auto-equalization is performed in source driver chips to optimize data reception, then data reception quality improves, but power supply voltage fluctuations increase
Solution Approach 1:
The patent implements a feedback mechanism where the bit error rate test results are fed back to the equalization control unit. This feedback loop allows the system to automatically adjust equalization parameters based on actual reception quality, optimizing data reception while keeping power consumption and voltage fluctuations within acceptable ranges by only adjusting equalization when necessary
Solution Approach 2:
The patent dynamically adjusts equalization parameters (such as equalization strength and timing) based on operating conditions rather than using fixed high-power equalization. By changing parameters adaptively based on signal quality and environmental conditions, the system maintains optimal data reception while minimizing power consumption and voltage fluctuations during equalization operations
Data Source
AI summary
A display driver chip includes an optimal equalization function and an optimal equalization method, by which image data having high quality may be provided to a display device. The display driver chip may comprise: a data reception unit that receives data; a clock data reconstruction unit that reconstructs an output signal of the data reception unit according to a clock signal; a bit error rate test unit that tests a bit error rate for reconstructed data and provides the result of the test; and an equalization option control unit that configures a condition for initial equalization, configures the number of optimal equalization steps and optional equalization steps to be added, on the basis of the provided test result, and feeds same back to the data reception unit.