Display Driving Chip Synchronization for Consistent High-Resolution Frames
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Solution Overview
Problem
High-resolution display panels require multiple processing chips, but existing designs may cause abnormal display due to asynchronous frame address changes among chips, leading to inconsistent display data.
Innovation Solution
A display driving device with a master and slave processing chips, using read/write synchronization signals to ensure synchronized caching and reading of display data into shared frame addresses, preventing asynchronous frame address changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple processing chips are used to drive high-resolution display panels, then the memory bandwidth and transmission interface requirements are met, but asynchronous frame address changes occur among chips causing abnormal display
Solution Approach 1:
A synchronization controller is introduced as an intermediary component that receives synchronization signals and distributes them to multiple processing chips. This mediator ensures all chips operate synchronously by coordinating their frame address changes, thereby maintaining display consistency while enabling the use of multiple chips for high-resolution output
2Productivity
If multiple processing chips are used to increase processing capacity, then high-resolution display requirements are met, but the system complexity increases due to synchronization requirements
Solution Approach 1:
The synchronization control functions of multiple processing chips are merged into a unified control mechanism. The synchronization controller consolidates the timing and coordination logic, allowing individual chips to focus on their primary processing tasks while the merged control system handles synchronization, thereby reducing overall system complexity
3Reliability
If frame addresses are shared among multiple processing chips, then display data consistency is maintained, but asynchronous changes still occur leading to abnormal display
Solution Approach 1:
A feedback mechanism is implemented where the synchronization controller monitors the operational state of each processing chip and adjusts synchronization signals in real-time. This feedback loop ensures that frame address changes occur simultaneously across all chips, preventing asynchronous changes while maintaining shared frame address consistency
Data Source
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AI summary
A display driving device, a control method therefor, and a display apparatus. The control method comprises: a main processing chip generates a read-write synchronization signal when buffering received display data, and each secondary processing chip receives the read-write synchronization signal (S202); in response to the read-write synchronization signal, the main processing chip buffers the received display data of the current frame image to be displayed to the frame address of a corresponding memory, and performs reading and processing on the buffered display data of a previous frame image to be displayed and then transmits to a display panel, and in response to the read-write synchronization signal, each secondary processing chip synchronously buffers the received display data of the current frame image to be displayed to the frame address of the corresponding memory, and synchronously performs reading and processing on the buffered display data of the previous frame image to be displayed and then transmits to the display panel (S203). By means of the read-write synchronization signal, the main processing chip and all the secondary processing chips are controlled to control the storage and read operations of the memory, and thus, the present invention can avoid that the processing chips share the frame address of the memory, and further can avoid the problem of abnormal image display due to multiple asynchronous processing chips.