Display Driving Circuit Layout for Flat Panel Bonding
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Solution Overview
Problem
The existing display device designs are limited by protruded bonding regions due to the assembly of signal circuits, which affect the profile and increase the risk of trace crossing.
Innovation Solution
The design involves a display device with a driving circuit substrate, a TFT array substrate, and a front plane laminate, where conductive pads are distributed averagely in the periphery region to avoid protrusion, and signal circuits are connected to pads based on their extension direction to reduce trace lengths and prevent crossing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If signal circuits are assembled to the same side of the panel in a bonding region, then electrical connection to IC is achieved, but the bonding region protrudes outwardly and limits the profile
Solution Approach 1:
The patent transitions from planar bonding region assembly to three-dimensional stacked substrate assembly. Multiple substrates (driving circuit substrate, TFT array substrate, front plane laminate) are stacked vertically with bonding regions distributed across different layers, converting a two-dimensional protrusion problem into a three-dimensional integrated structure that maintains electrical connectivity while achieving a flat profile.
Solution Approach 2:
The patent implements nested bonding regions where bonding areas of different substrates are positioned within the boundary of collectively formed boundaries. The driving circuit substrate bonding region, TFT array substrate bonding region, and front plane laminate bonding region are nested within each other's projected boundaries, creating a compact stacked structure without outward protrusion.
2Ease of manufacture
If bonding region is assembled on the periphery, then IC connection is achieved, but the protruded bonding region affects the display device profile
Solution Approach 1:
The patent moves the bonding operation from a single-plane periphery assembly to multi-layer vertical stacking. Bonding regions are distributed across multiple substrate layers in the vertical dimension, allowing IC connections to be established without creating horizontal protrusions that would affect the profile.
Solution Approach 2:
The patent employs asymmetric distribution of bonding regions across different substrate layers. Each substrate has its bonding region positioned at different locations and orientations, preventing symmetric protrusion and enabling a flat overall profile while maintaining all necessary connections.
3Reliability
If conductive traces extend across the panel, then signal circuits are connected, but trace crossing risk increases
Solution Approach 1:
The patent resolves trace crossing issues by routing conductive traces through the vertical stacking dimension. Different signal circuits are implemented on different substrate layers, allowing traces that would cross in a two-dimensional plane to be separated in three-dimensional space, eliminating crossing conflicts while maintaining connectivity.
Solution Approach 2:
The patent segments the signal circuit implementation across multiple substrate layers. Each substrate carries specific signal circuits, dividing the overall routing problem into separate layers where trace paths can be independently optimized without crossing conflicts between different signal paths.
Data Source
AI summary
A display device includes a display region and a periphery region surrounding the display region. The display device includes an driving circuit substrate, a TFT array substrate, a front plane laminate, and multiple conductive wires. The driving circuit substrate includes multiple first conductive pads. The TFT array substrate includes multiple second conductive pads. The TFT array substrate is located on the driving circuit substrate. The TFT array substrate is located between the driving circuit substrate and the front plane laminate. The conductive wires are electrically connected with the first conductive pads and the second conductive pads, respectively. The first conductive pads and the second conductive pads are located in the periphery region.