Display Device Circuit Layout for Frame Reduction
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Solution Overview
Problem
Conventional display devices with liquid crystal technology face challenges in maintaining display quality due to the visibility of frame regions between multiple units, which can lead to a deterioration in the continuity of the display when arranged side by side.
Innovation Solution
The solution involves a display device configuration with a circuit layer on a substrate that includes scanning signal line driving circuits distributed across multiple regions, allowing for a reduction in the frame region by overlapping these circuits with pixel electrodes, thereby minimizing the visible frame and maintaining display continuity when multiple units are arranged.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If multiple liquid crystal displays are arranged side by side to achieve a large screen, then the display size is increased, but the frame regions between units become visible and display continuity deteriorates
Solution Approach 1:
The invention moves the scanning signal line driving circuits from the peripheral frame regions to the inner display region, utilizing the vertical space above the pixel electrodes. This dimensional relocation allows the circuits to overlap with the pixel electrodes in the vertical direction while maintaining horizontal continuity of the display region, thereby eliminating visible frame regions between multiple display units.
Solution Approach 2:
The scanning signal line driving circuits are nested within the display region by positioning them to overlap with the pixel electrodes in the vertical direction. The circuits are arranged in the vertical space above the pixel electrodes, effectively nesting the circuit layer within the display area and eliminating the need for separate peripheral frame regions.
2Ease of manufacture
If scanning signal line driving circuits are arranged in peripheral frame regions, then circuit layout is simplified, but the frame regions become visible and display continuity is compromised
Solution Approach 1:
The invention resolves the layout complexity by arranging scanning signal lines in parallel rows across the display region and positioning driving circuits at specific locations above pixel rows. This systematic arrangement in the vertical dimension simplifies the connection architecture while eliminating peripheral frame regions.
Solution Approach 2:
The display region is divided into multiple scanning signal line groups, with driving circuits segmented and positioned at specific locations above different pixel rows. This segmentation allows for modular circuit layout while maintaining overall display continuity and eliminating visible frame regions.
3Object-generated harmful factors
If frame regions are reduced by overlapping circuits with pixel electrodes, then display continuity is improved, but circuit layout complexity increases
Solution Approach 1:
The invention manages circuit layout complexity by utilizing the vertical dimension above pixel electrodes. Scanning signal lines are arranged in parallel rows, and driving circuits are positioned at specific vertical locations, creating a systematic three-dimensional layout that appears complex but follows regular patterns for ease of manufacturing.
Data Source
AI summary
A display device includes a first substrate; and a circuit layer arranged on the first substrate and comprising a first scanning signal line driving circuit arranged on the side of a first side of the first substrate, a second scanning signal line driving circuit arranged on the side of a second side, a third scanning signal line driving circuit arranged between the first scanning signal line driving circuit and the second scanning signal line driving circuit, and each of a plurality of pixel circuits including a first pixel circuit and a second pixel circuit, the first pixel circuit being arranged in a region between the first scanning signal line driving circuit and the third scanning signal line driving circuit, and the second pixel circuit being arranged in a region between the third scanning signal line driving circuit and the second scanning signal line driving circuit.