Display Device Circuit Layout for Reduced Non-Display Area
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing display devices have a significant non-display area that hinders their further reduction in size and thickness, limiting their applications.
Innovation Solution
The display device design incorporates a test circuit opposite the fan-out unit with the display area in between, featuring a data distribution circuit partially circling the outer side of the display area, and a common power supply line that surrounds the display area with one open side, along with a symmetrical layout to minimize the non-display area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the non-display area is reduced, then the display device becomes more compact and thinner, but the layout of circuits and wirings becomes more complex
Solution Approach 1:
The patent implements nesting by positioning the test circuit in the non-display area such that it overlaps with the fan-out unit in the vertical direction. The test circuit is arranged between the display area and the fan-out unit, with its wirings extending into the non-display area while remaining spatially nested within the existing structure. This nesting approach allows the test circuit to share space with other components, thereby reducing the overall non-display area without significantly increasing layout complexity.
Solution Approach 2:
The patent applies dimensionality change by transitioning from a two-dimensional planar layout to a three-dimensional stacked arrangement. The test circuit is positioned in the vertical dimension within the non-display area, overlapping with the fan-out unit. This vertical stacking allows multiple circuits to occupy the same horizontal footprint at different heights, effectively reducing the horizontal non-display area while managing complexity through vertical integration rather than horizontal expansion.
2Length of stationary object
If the peripheral area is minimized, then the display device achieves thinner profile, but the routing of data lines and power supply lines becomes more difficult
Solution Approach 1:
The patent segments the non-display area into distinct functional zones: a first non-display area containing the test circuit and a second non-display area containing the fan-out unit. The test circuit is positioned opposite the fan-out unit with the display area in between, creating separate routing paths. This segmentation allows data lines and power supply lines to be routed independently through different regions, simplifying the routing process while minimizing the overall peripheral area.
Solution Approach 2:
The display area serves as an intermediary zone between the test circuit and the fan-out unit. By positioning the test circuit opposite the fan-out unit with the display area in between, the patent creates a spatial buffer that facilitates routing. The display area acts as a mediator that allows wires to be routed around the periphery without direct interference between the test circuit and fan-out unit, making the routing process easier while maintaining a compact peripheral area.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A display device including: a substrate including a display area and a peripheral area adjacent to the display area; a plurality of data lines extending in a first direction in the display area; a fan-out unit arranged in the peripheral area and connected to the plurality of data lines; a first signal line arranged in the peripheral area; and a common power supply line arranged in the peripheral area and overlapping the fan-out unit.