Display Pixel Circuit Layout to Minimize Parasitic Capacitance
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Solution Overview
Problem
Parasitic capacitance between conductive layers in display devices degrades display quality, and existing solutions often require additional shielding layers which can complicate the display device's structure and functionality.
Innovation Solution
The display device is designed with a specific layout of conductive layers and active patterns where the capacitor conductive pattern is connected to the gate electrode of the driving transistor through a control pattern, preventing exposure to upper conductive layers and thus reducing parasitic capacitance without the need for additional shielding layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional shielding layers are added to prevent parasitic capacitance, then display quality is improved, but device complexity increases
Solution Approach 1:
The patent extracts and removes the capacitor conductive pattern from the conventional conductive layer arrangement by positioning it between the first and second conductive layers rather than within a single layer. This extraction eliminates the need for additional shielding layers while maintaining parasitic capacitance prevention, thereby resolving the contradiction between display quality improvement and structure simplification
Solution Approach 2:
The patent changes the dimensional arrangement of the capacitor conductive pattern by positioning it in an intermediate space between conductive layers rather than within a planar layer. This spatial repositioning in the vertical dimension allows the capacitor to function without requiring additional lateral shielding structures, thus improving display quality while maintaining structural simplicity
2Ease of manufacture
If capacitor conductive pattern is exposed to upper conductive layers, then manufacturing is simpler, but parasitic capacitance increases
Solution Approach 1:
The patent implements a nested structure where the capacitor conductive pattern is positioned within the vertical stack between the first and second conductive layers. This nesting arrangement allows the capacitor to be integrated into the existing multi-layer structure without requiring additional exposed layers, thereby preventing parasitic capacitance while maintaining manufacturing simplicity through the use of existing fabrication processes
Data Source
AI summary
A display device includes: a substrate; a first conductive layer on the substrate and including a lower conductive pattern and a capacitor conductive pattern spaced apart from the lower conductive pattern in a plan view; an active layer on the first conductive layer, partially overlapping the lower conductive pattern and the capacitor conductive pattern in the plan view, and including a driving active pattern defining a storage capacitor together with the capacitor conductive pattern; a second conductive layer on the active layer, partially overlapping the lower conductive pattern and the driving active pattern in the plan view, and including a control pattern defining a driving transistor together with the driving active pattern; and a third conductive layer on the second conductive layer and including an anode electrode partially overlapping the lower conductive pattern in the plan view.