Display Device Circuit Areas and Sub-Pixels
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Solution Overview
Problem
Display devices face issues with the ripple phenomenon and dim phenomenon due to parasitic capacitance caused by overlapping wiring lines, leading to luminance non-uniformity and light leakage, which increase manufacturing costs and degrade display quality.
Innovation Solution
The display device is designed with a substrate that includes reference lines and data lines disposed on either side of circuit areas, preventing overlap and minimizing parasitic capacitance, and sub-pixels are arranged in a zigzag pattern to reduce light leakage and color coordinate distortion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the number of wiring lines is increased to achieve higher resolution, then the resolution is improved, but the parasitic capacitance between overlapping wiring lines increases causing ripple phenomenon
Solution Approach 1:
The patent transitions from a planar arrangement where data lines and common lines overlap in the same layer to a three-dimensional arrangement where they are separated in different layers. The data line is disposed in a first layer while the common line is disposed in a second layer below it, eliminating parasitic capacitance caused by overlapping while maintaining high resolution display capabilities
Solution Approach 2:
The patent segments the wiring structure into multiple independent layers, with data lines in one layer and common lines in another layer. This segmentation allows each wiring type to be independently routed without interference, reducing parasitic capacitance between data and common lines while maintaining the required number of wiring lines for high resolution
2Area of stationary object
If wiring lines are disposed in a limited area, then the device area is reduced, but the wiring lines overlap causing ripple phenomenon
Solution Approach 1:
The patent utilizes vertical layering to separate data lines and common lines, allowing both types of wiring to be disposed in a compact planar area without overlapping. The data line in the first layer and common line in the second layer can be closely spaced without causing parasitic capacitance, thus reducing the device area while eliminating ripple phenomenon
3Object-affected harmful factors
If data line and common line are disposed to prevent overlap, then parasitic capacitance is reduced, but the wiring layout complexity increases
Solution Approach 1:
The patent simplifies the wiring layout by using vertical layering to automatically separate data lines and common lines. This three-dimensional arrangement eliminates the need for complex planar routing strategies to avoid overlap, as the layers themselves provide natural separation, thus reducing parasitic capacitance without significantly increasing layout complexity
Data Source
AI summary
A display device can include a substrate on which reference lines extending in a first direction are disposed, first sub pixels which include a first circuit area disposed at one side of the reference lines and a first emission area disposed at another side of the reference lines, second sub pixels which include a second emission area disposed at one side of the reference lines and a second circuit area disposed at another side of the reference lines, first data lines which extend in the first direction and are disposed to be spaced apart from the reference lines, and second data lines which extend in the first direction and are disposed to be spaced apart from the reference lines.