Display Clock Recovery Circuit With Adaptive Delay Voltage Control
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Solution Overview
Problem
Existing clock data recovery circuits in displays are limited by a multi-stage delay chain using inverters, which restricts the operating frequency and bandwidth for recovering data from high-speed clock data signals.
Innovation Solution
A clock data recovery circuit that includes a delay line with multiple stages of delay units and a mode generator. The mode generator compares the unit delay time between input and output delayed clocks with a preset reference delay time, adjusting the driving voltage of the delay units between two different levels to generate delayed clocks suitable for wide bandwidth operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a multi-stage delay chain using inverters is used to recover the clock, then the clock recovery function is achieved, but the operating frequency and bandwidth are limited
Solution Approach 1:
The patent changes the driving voltage parameter of the delay units between two different levels (first driving voltage and second driving voltage) based on the comparison result between unit delay time and reference delay time. This parameter change enables the delay chain to operate at different frequency ranges, thereby improving the operating frequency and bandwidth without fundamentally changing the delay chain structure.
Solution Approach 2:
The patent introduces dynamic adjustment capability to the delay chain by making the driving voltage selectable between two levels based on real-time comparison of delay time. This dynamic adjustment allows the system to adapt to different operating conditions and frequency requirements, resolving the contradiction between achieving high operating frequency and maintaining structural simplicity.
2Adaptability or versatility
If the driving voltage of delay units is fixed, then the circuit structure is simple, but the bandwidth for data recovery is limited
Solution Approach 1:
The system performs self-adjustment by automatically comparing the unit delay time with the reference delay time and selecting the appropriate driving voltage level based on this comparison. This self-service mechanism enables the delay chain to adapt to different bandwidth requirements without external intervention, achieving wide bandwidth while keeping the control mechanism relatively simple.
Solution Approach 2:
The patent implements a feedback mechanism where the mode generator continuously compares the unit delay time between input and output delayed clocks with a preset reference delay time, and uses this comparison result to control the selection of driving voltage. This feedback loop enables the system to maintain optimal performance across different operating conditions, achieving wide bandwidth adaptability.
3Reliability
If a separate oscillator is used to generate the clock, then the clock signal is stable, but the device complexity increases
Solution Approach 1:
The delay chain circuit recovers the clock signal directly from the input clock without requiring a separate oscillator, performing the clock generation function itself through its delay units and voltage control mechanism. This self-service approach eliminates the need for additional oscillator components while maintaining clock signal stability through the controlled delay mechanism.
Solution Approach 2:
The delay chain circuit performs multiple functions: it delays the input clock to generate delayed clocks, recovers the clock signal, and adapts to different frequency ranges through voltage selection. By making the delay chain multi-functional, the patent eliminates the need for a separate oscillator, reducing device complexity while maintaining clock stability.
Data Source
AI summary
A clock data recovery circuit of a display suitable for recovering a clock from a clock data signal. The clock data recovery circuit includes a clock recovery circuit configured to delay an input clock through delay units of multiple stages, and output delayed clocks from the delay units, respectively; and a data recovery circuit configured to recover data of a clock data signal using a recovered clock selected among the delayed clocks.