Display Control Circuitry Clock Calibration via Segmented Timing
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Solution Overview
Problem
Electronic devices with displays face challenges in coordinating the timing of data for display with control signals for pixel rows and columns, leading to potential errors due to differences in system and display 1H times, especially with temperature-induced oscillator frequency changes.
Innovation Solution
Incorporating an internal oscillator and counters in the display control circuitry to decouple display 1H timing from system timing, allowing for real-time correction of timing errors and ensuring accurate frame synchronization by maintaining current-row and current-frame counts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the display control circuitry uses system timing for display 1H timing, then the system can operate with a longer vertical blanking period for data processing, but timing errors accumulate due to differences between system line time and display line time
Solution Approach 1:
The patent segments the timing control into two independent parts: system timing for data processing and display timing for pixel operation. The display control circuitry includes a display timing controller that generates display 1H timing independently from system 1H timing, allowing each to operate optimally without interfering with the other's precision requirements
Solution Approach 2:
The patent introduces an intermediary display timing controller that acts as a buffer between the system timing and display timing. This intermediary component receives system data during vertical blanking periods while maintaining independent display timing to ensure precise pixel row/column operation without accumulating timing errors
2Measurement precision
If the display control circuitry uses an internal oscillator to decouple display timing from system timing, then timing accuracy is improved, but the device complexity increases due to additional counting circuits
Solution Approach 1:
The patent implements multi-functional counting circuits that serve multiple purposes: they count display 1H periods for timing synchronization, count pixel rows and columns for address generation, and provide feedback for timing error correction. This universal usage of counting circuits reduces the need for separate dedicated circuits for each function
Solution Approach 2:
The patent employs feedback mechanisms where the display timing controller continuously monitors the relationship between system timing and display timing, and automatically adjusts display 1H timing to compensate for drift or errors. This closed-loop feedback system maintains high timing accuracy without requiring overly complex hardware
Data Source
AI summary
Aspects of the subject technology relate to electronic devices with displays. A display may include display control circuitry including an internal oscillator and one or more counters. The counters may be used to calibrate a display line time to a system line time to ensure that each displayed frame is synchronized with received display data frames from system circuitry for the electronic device. The counters may include a first counter that maintains a current-row count during operation of a current row of display pixels during a current display frame and a second counter that maintains a current-frame count that indicates a number of counts accumulated during the current display frame. The current-row count and the current-frame count may be referenced to the system line time during operation of each pixel row to remove any errors accumulated during operation of the previous pixel rows.