Display Clock Synchronization for Seamless Channel Switching
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Solution Overview
Problem
During channel switching in digital display devices, the timing mismatch between input and output video signals often results in line buffer overflow or underflow, leading to abnormal panel display due to unsynchronized frame rates and phases across different channels.
Innovation Solution
A display control device comprising a first measuring circuit for frequency detection, a second measuring circuit for phase deviation measurement, a determining circuit for generating control signals, a timing controller, and a clock generator to adjust and synchronize the display clock and timing signals, ensuring smooth channel switching by compensating for frequency and phase deviations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If frame synchronization technology resets the DVS signal according to the IVS signal, then the timing control is simplified, but during channel switching the frequencies and phases of IVS signals from different channels are not synchronized, causing DVS signal timing mismatch and panel display failure
Solution Approach 1:
The patent applies preliminary action by measuring the frequency and phase of the IVS signal in advance before channel switching occurs. The measuring circuit captures these parameters proactively, so when channel switching happens, the system already has the necessary timing information to adjust the DVS signal appropriately, preventing display failures without adding complex real-time control mechanisms.
2Ease of operation
If frame rate conversion buffers at least one frame in the frame buffer, then timing control of output image signal becomes independent from input image signal, but the chip area increases due to large storage capacity requirements
Solution Approach 1:
The patent changes the approach from buffering entire frames to buffering only partial frame data (less than one frame) in the line buffer. By adjusting the buffering parameter from full-frame to partial-frame, the system maintains timing control flexibility while significantly reducing the required storage capacity and chip area.
Solution Approach 2:
Instead of buffering the complete frame data, the system uses partial buffering with the line buffer storing only the necessary portion of frame data (less than one frame). This partial action approach provides sufficient timing control independence while minimizing the storage requirements and chip area occupation.
Data Source
AI summary
The invention discloses a display control device and method thereof. The display control device and method thereof utilize the phase deviation and the frequency deviation between the output signal and the input signal caused during channel switching to provide converting time acceptable by a display device and to achieve the objective of balancing the data stream transmission.